Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.

Abstract: Compact light-weight on-board three-port power electronic system built in various configurations of triple-active-bridge-derived topologies, including modular implementations, with control strategies capable of bi-directional power transfer among the three ports of the power electronic system, including simultaneous charging of a high voltage (HV) battery and a low voltage (LV) battery from a single phase power grid or a three-phase power grid with minimized reactive power and active circulating current, with ensured soft-switching for MOSFET devices, and with enhanced synchronous rectification and reduced power losses.

Abstract: Embodiments include herein are directed towards a method for dynamic voltage and frequency scaling (DVFS) based timing signoff associated with an electronic design environment. Embodiments may include receiving, using a processor, an electronic design and specifying, via a graphical user interface, a voltage sweep for each power net associated with the electronic design. Embodiments may further include specifying, via the graphical user interface, at least one voltage sweep to be excluded from analysis. Embodiments may also include automatically generating DVFS configurations based upon, at least in part, the voltage sweep for each power net and the at least one voltage sweep to be excluded from analysis.

Abstract: Example test generation systems and methods are described. In one implementation, a hardware test suite generator includes a script reader that receives a test definition script and parses the test definition script. A test generator receives the parsed test definition script from the script reader and creates a test suite. A template reader receives a test definition template and parses the test definition template. A code generator receives the parsed test definition script from the script reader and receives the parsed test definition template from the template reader.

Abstract: A standard cell establishment method is disclosed. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully.

Abstract: A battery-disconnect circuit may include a latch, a battery-disconnect subcircuit, and a power-enable subcircuit. The battery-disconnect subcircuit may be configured to control current leakage. The battery-disconnect subcircuit may be connected to the latch. The latch may be configured to maintain a power supply state of the battery-disconnect subcircuit, a no-power supply state of the battery-disconnect subcircuit, or both. The power-enable subcircuit may be connected to the battery-disconnect subcircuit. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the power supply state based on an enable signal. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the no-power supply state based on an off signal.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

Abstract: Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.

Abstract: A parallel plate capacitor structure in an integrated circuit has a first plate and a second plate separated by an insulator, such as a dielectric. Both plates are connected to an interconnect structure at a plurality of connection points. The area of the first plate that overlaps with the second plate is identified. This overlap region does not include any connection points on the first plate. For this overlap region, the lumped element model for the first plate includes nodes on the edge of the overlap region (edge nodes), and lumped resistances between the edge nodes and the node connected to the lumped capacitance. In one embodiment, the lumped element model also includes a common node, all of the edge nodes are connected to the common node by lumped resistances, and the common node is connected by a negative resistance to the lumped capacitance.

Abstract: A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.

Abstract: An IC design data base generating method, including: receiving a condition parameter, which comprises a process parameter and an operating parameter range comprising at least one operating parameter; and testing at least one cell according to the process parameter and the operating parameter range to generate a delay value data base. The delay value data base comprises a plurality of delay values, wherein the plurality of delay values for an identical cell correspond to the operating parameter range with an identical type but different value. An IC design method using the delay value data base is also disclosed.

Abstract: A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A method for designing a power network is provided and includes: initializing via widths and power-trace widths; determining whether utilization rates of first, second and third routing tracks are respectively equal to first, second and third values; when said utilization rate of said first routing tracks is not equal to said first value, adjusting said distance between first and second power traces until said utilization rate thereof is equal to said first value; when said utilization rate of said second routing tracks is not equal to said second value, adjusting said distance between third and fourth power traces until said utilization rate thereof is equal to said second value; and when said utilization rate of said third routing tracks is not equal to said third value, adjusting said distance between fifth and sixth power traces until said utilization rate thereof is equal to said third value.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.

Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.

Abstract: An FPGA system includes: an FPGA configured such that a partial reconfiguration is executable; and an external storage medium that is positioned outside of the FPGA and stores configuration data that is readable by the FPGA. The external storage medium stores first configuration data indicating a configuration of a circuit that is not subject to the partial reconfiguration and a second configuration data indicating a configuration of a circuit that is subject to the partial reconfiguration. The first configuration data includes configuration data indicating a configuration of a reconfiguration activation circuit for reading the second configuration data from the external storage medium and deploying the configuration indicated by the second configuration data.

Abstract: Machine assisted system and method for performing dynamic thermal management (DTM) analysis are described. In one embodiment, the method can include receiving a power profile associated with IP blocks in an integrated circuit (IC) system modeled by a Krylov reduced order model (ROM). The power profile can represent power consumption of each of the blocks based on a predefined operating scenario. The method can additionally include evaluating the temperature of each of the blocks of the IC system for the current time step based on the power profile and the Krylov ROM. The method can further include calculating new power values based on the current temperature field of each of the blocks of the IC system, wherein the power profile can be updated with the new power value for the temperature of each of the blocks of the IC system for the next time step.