Abstract: Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Abstract: A method, system and computer program product for appending abstractions to a testbench used for verifying the design of an electronic circuit. According to an embodiment of the invention, a method comprises identifying a set L of one or more support properties l for a set P of one or more properties p for a given electronic circuit; computing a plurality of hardware signals s of the given electronic circuit; and creating a plurality of abstract signals ABS, including declaring a fresh abstract signal abs_s for each of the hardware signals s, and creating a fresh abstract signal abs_l for each of the support properties l of the set L; for each of the properties p of the set P, creating an abstract property version abs_p; and appending the abstract signals ABS and the abstract property abs_p to the testbench to form an appended testbench.

Abstract: An electromagnetic resonance-type wireless power transmitter according to one embodiment of the present invention may comprise: a power conversion unit including a converter capable of converting a voltage received from a power supply unit into a particular voltage; a power transmission unit including a wireless power transmission coil for receiving the particular voltage from the power conversion unit and wirelessly transmitting power, using a particular resonance frequency; a communication unit capable of performing data communication with a wireless power receiver; and a control unit for controlling the power conversion unit, the power transmission unit, and the communication unit, wherein the wireless power transmission coil may comprise an outer coil part having a first loop shape, and an inner coil part disposed within the first loop shape and having a second loop shape, the direction of a current flowing through the outer coil part may be opposite to that of a current flowing through the inner coil par

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.

Abstract: Embodiments are disclosed for routing a cell of a semiconductor chip, the cell being represented by a matrix, encoding first tracks of the cell as columns of the matrix and second tracks of the cell as rows of the matrix, respectively. The method includes performing a sweep operation on the matrix, the sweep operation including generating an index structure indexed by columns of the matrix, the index structure including information on candidate cut shapes that can be placed in a particular column of the matrix. Additionally, the method includes recursively placing cut shapes into the cell based on the index structure, one recursion of the placing including finding a possible cut shape and recursively placing the remaining cut shapes.

Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: In an approach to simulating an electronic device, a copy of a design under test is created. A delayed buffer for the copy is created, where the inputs to the design under test are stored in the delayed buffer. A test program is run on the design under test and the copy, where the test program running on the copy is delayed in time by the delayed buffer. Responsive to determining that an event has occurred on the design under test, the test program on the copy is halted. The cause of the event is determined by using the inputs stored in the delayed buffer to scan the copy.

Abstract: A routing assembly for an electronic device has a plurality of connectors ports and each of the connector ports contains a first connector connected to one or more cables. Cables are directly terminated, at first ends thereof, to terminals of the first connectors and the cables can be embedded in a routing substrate. The routing substrate has an opening which accommodates a chip package. Second ends of the cables are terminated to second connectors arranged in the package opening and the second connectors are in turn connected to third connectors that are connected to the chip package.

Abstract: A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.

Abstract: Technologies are described herein to track information storage resources in a quantum circuit during compile time or runtime of a program by which quantum algorithms are built.

Abstract: A method comprising using at least one hardware processor for: running a Monte Carlo simulation of possible integrated circuit (IC) process variations of each of a plurality of IC cell types, wherein each of the plurality of IC cell types is defined by multiple specific transistors and multiple specific interconnects; based on the results of the Monte Carlo simulation, creating a library of IC cell types and their corresponding behavioral values for each of the possible IC process variations, and storing the library in a non-transient memory; receiving an IC design embodied as a digital file; correlating the received IC design with the library; and predicting a frequency distribution and a power distribution of ICs manufactured according to the IC design.

Abstract: According to an embodiment, a method for forming an electronic circuit is provided including forming a netlist of an electronic circuit having a multiplicity of flip-flops, selecting groups of flip-flops from the multiplicity of flip-flops, providing, for each selected group of flip-flops, an error detection circuit for the flip-flops of the group and forming the electronic circuit based on the netlist to include the provided error detection circuits.

Abstract: The computer processor identifies a first shared set of input ports that are common to a first hardware model and a second hardware model and a second shared set of input ports that are common to a first reference model and a second reference model. The computer processor selects logic of the first hardware model and logic of the second hardware model that are each traceable to the first shared set of input ports and selects logic of the first reference model and logic of the second reference model that are each traceable to the second shared set of input ports. The computer processor determines that the logic of the second hardware model and the logic of the second reference model have verified logic by determining that the logic of the first hardware model is equivalent to the logic of the second hardware model and the logic of the first reference model is equivalent to the logic of the second reference model.

Abstract: A compaction circuit in an emulation system may store in a data array emulation data that may be read in subsequent emulation steps. For each emulation step, the compaction circuit may receive keeptags from a local control store word of the emulation step and store portions of emulation data identified by the keeptags. The keeptags in the control store words may be inserted by a compiler based upon whether a corresponding read port of emulation processor reads the stored data in the subsequent steps. The compaction circuit may also translate the logical read address of the stored data to a physical read address in the shared data array. A dynamic modification engine may enable dynamic modification of netlists while using the compacted data array. In response to a request, the dynamic modification engine may modify one or more keeptags and update read addresses in the control store words.

Abstract: A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: The present invention relates to a wireless charging device including a communication signal compensator, a communication signal compensator comprises a power detector configured to detect a magnitude of a communication signal received through each of the plurality of antennas, and a control unit configured to acquire a communication signal having the greatest signal magnitude as the detection result, select an antenna corresponding to the communication signal having the greatest signal magnitude among the plurality of antennas, and transmit, to the coupling antenna, a switch control signal for controlling the switch to be connected to the selected antenna.

Abstract: The optimization of circuit parameters of variational quantum algorithms is a challenge for the practical deployment of near-term quantum computing algorithms. Embodiments relate to a hybrid quantum-classical optimization methods. In a first stage, analytical tomography fittings are performed for a local cluster of circuit parameters via sampling of the observable objective function at quadrature points in the circuit parameters. Optimization may be used to determine the optimal circuit parameters within the cluster, with the other circuit parameters frozen. In a second stage, different clusters of circuit parameters are then optimized in “Jacobi sweeps,” leading to a monotonically convergent fixed-point procedure. In a third stage, the iterative history of the fixed-point Jacobi procedure may be used to accelerate the convergence by applying Anderson acceleration/Pulay's direct inversion of the iterative subspace (DIIS).