Abstract: To obtain an imaging unit, a lens barrel, and a portable terminal which can effectively suppress spring-back of solid-state imaging elements, while facilitating height lowering thereof. An imaging unit includes: a solid-state imaging element; and an imaging lens for forming a subject image on a photoelectric conversion part of the solid-state imaging element. An imaging surface of the solid-state imaging element is curved in a manner that a peripheral side is inclined toward an object side relative to a screen center. The imaging lens constrains the solid-state imaging element to prevent a radius of curvature of the imaging surface from varying. Thus, field curvature, distortion aberration, and comatic aberration are appropriately corrected.

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Abstract: A semiconductor device includes a leadframe, a semiconductor chip mounted on the leadframe, and an encapsulation resin covering the leadframe and the semiconductor chip. The leadframe includes a terminal having a pillar shape. The terminal includes a first end surface, a second end surface facing away from the first end surface, and a side surface extending vertically between the first end surface and the second end surface. The side surface is stepped to form a step surface facing away from the second end surface and having an uneven surface part formed therein. A first portion of the terminal extending from the first end surface toward the second end surface and including the step surface is covered with the encapsulation resin. A second portion of the terminal extending from the first portion to the second end surface projects from the encapsulation resin.

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

Abstract: In a method for manufacturing a semiconductor device by using a gate replacement technology, a gate space constituted by dielectric material portions, in which a semiconductor fin channel layer is exposed, is formed. The surfaces of the dielectric material portions are made hydrophobic. A first dielectric layer is formed on the semiconductor fin channel layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A surface of the formed first dielectric layer is hydrophilic. A first conductive layer is formed over the first dielectric layer, while maintaining the surfaces of the dielectric material portions hydrophobic. A second conductive layer is formed over the first conductive layer and on the hydrophobic surfaces of the dielectric material portions, thereby filling the gate space.

Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, such as proximity sensing or optical ranging devices. One embodiment is directed to an optical sensor package that includes a substrate, a sensor die coupled to the substrate, a light-emitting device coupled to the substrate, and a cap. The cap is positioned around side surfaces of the sensor die and covers at least a portion of the substrate. The cap includes first and second sidewalls, an inner wall having first and second side surfaces and a mounting surface, and a cover in contact with the first and second sidewalls and the inner wall. The first and second side surfaces are transverse to the mounting surface, and the inner wall includes an opening extending into the inner wall from the mounting surface. A first adhesive material is provided on the sensor die and at least partially within the opening, and secures the inner wall to the sensor die.

Abstract: Disclosed are an oxide semiconductor-based transistor and a method of manufacturing the same. The oxide semiconductor-based transistor includes: a substrate provided with a bottom electrode; an insulator layer formed on the substrate; an active layer formed on the insulator layer; an electron transport layer formed on the active layer; and a top electrode formed on the electron transport layer. Since the oxide semiconductor-based transistor has a hybrid channel of PBD formed along with indium-zinc oxide (IZO), it is possible to improve mobility of electric charges and stability of electric devices and control a threshold value.

Abstract: Provided is a semiconductor device including: a first transistor over a substrate, the first transistor having a gate electrode, an oxide semiconductor film, and a gate insulating film between the gate electrode and the oxide semiconductor film; an insulating film over the first transistor, the insulating film having a first film and a second film over the first film; and a terminal electrically connected to the oxide semiconductor film through an opening portion in the insulating film. The insulating film has a first region in contact with the terminal, and the first region has an oxygen composition larger than that in another region of the insulating film.

Abstract: Electronic devices and methods of producing such electronic devices are provided. In an exemplary embodiment, a method of producing an electronic device includes forming a protected circuit and an ESD circuit, where the ESD circuit is configured to discharge an electrostatic discharge (ESD) to a ground such that the ESD bypasses the protected circuit. An ESD transistor is formed in the ESD circuit, where the ESD transistor includes a source and a drain. The ESD transistor also includes a gate with a gate width perpendicular to a gate length, where the gate length is measured across the gate from the source to the drain. A trigger voltage of the ESD transistor is set by adjusting the gate width.

Abstract: An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Abstract: An electronic device may have control circuitry coupled to input-output devices such as a display. A flexible input-output device may be formed from an elastomeric substrate layer. The substrate layer may have signal paths to which components are mounted. Openings may be formed in the elastomeric substrate layer between the signal paths to create a stretchable mesh-shaped substrate. The electrical components may each include an interposer having solder pads soldered to the elastomeric substrate. Electrical devices such as micro-light-emitting diodes may be soldered to the interposers. The electrical components may also include electrical devices such as sensors and actuators. A stretchable lighting unit may have a stretchable light guide illuminated by a stretchable light source.

Abstract: Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

Abstract: An integrated circuit (IC) including at least one transistor having a metal-oxide-semiconductor (MOS) gate includes a substrate having a semiconductor surface. The transistor includes at least one trench isolation region in the semiconductor surface. Local oxidation of silicon (LOCOS) regions extend from within the semiconductor surface inside the trench isolation region defining a first LOCOS-free region and at least a second LOCOS-free region. A gate electrode is between the first LOCOS-free region and second LOCOS-free region including over a flat portion of a first of the LOCOS regions as its gate dielectric (LOCOS gate oxide). A first doped region is in the first LOCOS-free region and a second doped region is in the second LOCOS-free region on respective sides of the gate electrode both doped a first dopant type. A recessed channel region for the transistor is between the first and second doped regions under the LOCOS gate oxide.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: A power semiconductor package includes a first group of semiconductor dies attached to a first side of a substrate and evenly distributed over a width of the substrate and a second group of semiconductor dies attached to the first side of the substrate and evenly distributed over the substrate width. Each die in the first and second groups has all terminals at one side which is attached to the first side of the substrate and an insulated or isolated face at a side opposite the side with the terminals. A first intermediary metal layer of the substrate forms a first DC terminal. A second intermediary metal layer of the substrate forms a second DC terminal. These intermediary metal layers are insulated from one another and form a parallel plate waveguide. Additional power semiconductor package embodiments are described.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface on an opposite side thereof, and having a sensor therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at said one side of the primary surface of the first semiconductor layer, an insulating layer formed between the first semiconductor layer and the second semiconductor layer, and being disposed on the primary surface of the first semiconductor layer, and a charge-attracting semiconductor layer of the first conductivity type configured to attract electrical charges generated in the insulating layer when a fixed voltage is supplied to the charge-attracting semiconductor layer.

Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the MIM capacitor are provided. The MIM capacitor structure includes a substrate. A MIM capacitor is formed on the substrate. The MIM capacitor includes a U-shaped electrode having a first portion. The MIM capacitor also includes an inverted U-shaped electrode. The first portion of the U-shaped electrode is clamped by the inverted U-shaped electrode. The MIM capacitor further includes an insulating film between the U-shaped electrode and the inverted U-shaped electrode.

Abstract: A light-emitting device package includes a supporting substrate, a light-emitting device on the supporting substrate, an adhesive layer on at least a portion of a side surface or lower surface of the light-emitting device, the adhesive layer connecting the light-emitting device to the supporting substrate, and an air layer in a space defined by the supporting substrate, the light-emitting device, and the adhesive layer.

Abstract: Disclosed herein are multi-layered optically active regions for semiconductor light-emitting devices (LEDs) that incorporate intermediate carrier blocking layers, the intermediate carrier blocking layers having design parameters for compositions and doping levels selected to provide efficient control over the carrier injection distribution across the active regions to achieve desired device injection characteristics. Examples of embodiments discussed herein include, among others: a multiple-quantum-well variable-color LED operating in visible optical range with full coverage of RGB gamut, a multiple-quantum-well variable-color LED operating in visible optical range with an extended color gamut beyond standard RGB gamut, a multiple-quantum-well light-white emitting LED with variable color temperature, and a multiple-quantum-well LED with uniformly populated active layers.