Patents Examined by Brian E. Hearn
  • Patent number: 5468686
    Abstract: In a dry etching system, a method of cleaning an etching chamber allows a series of steps of introducing a wafer, selectively dry-etching an aluminum film provided on the wafer, cleaning the etching chamber by etching gas containing oxygen gas and capable of removing remaining chlorine, and ashing resist to be executed continuously with each of consecutive wafers without exposing them to the atmosphere. The etching and cleaning steps are completed within a period of time necessary for the ashing step. This not only protects the resulting aluminum wirings on the wafers from corrosion but also saves time otherwise consumed by the cleaning step, thereby increasing the throughput of the system.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: November 21, 1995
    Assignee: NEC Corporation
    Inventor: Hiedaki Kawamoto
  • Patent number: 5468677
    Abstract: An isolation structure of a semiconductor device including a channel stop diffusion region selectively formed on a portion of a single crystalline silicon substrate disposed beneath an edge of a field oxide film formed on the substrate, thereby capable of selectively increasing, irrespective of a pattern size of the field region, a channel ion concentration at an edge of a field region where the field region is connected to an active region and which region is a weak area serving to decrease a channel stop ion concentration at an interface between the field oxide film and the silicon substrate and to decrease a threshold voltage of a field transistor due to a small thickness thereof and thereby locally increasing the threshold voltage. By the local increase in threshold voltage, it is possible to prevent a degradation in insulating characteristic of the field transistor with a small pattern size.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: November 21, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Young K. Jun
  • Patent number: 5468680
    Abstract: A device and a method for interrupting the continuity of a conductor and linking a pair of conductors are disclosed. The device is a three-terminal fuse having first and second terminals initially connected by a conductor and a third terminal separated from the conductor at a breakpoint of the conductor by an insulator. By applying a voltage across the third terminal or control terminal and the conductor, a transient conductive link is formed between the conductor and the control terminal. If sufficient current is provided through the transient link, heating of the link causes the metal of the conductor to melt and boil away, thus interrupting the continuity of the conductor.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: November 21, 1995
    Assignee: Massachusetts Institute of Technology
    Inventor: Simon S. Cohen
  • Patent number: 5466617
    Abstract: Body portions (36) of semiconductor crystalline silicon material of sufficient quality to form high-mobility TFTs (thin-film transistors) and other semiconductor devices of a driver circuit are formed by depositing on a substrate (14) a layer of insulating silicon-based non-stoichiometric compound material (32) and then converting this material (32) into the semiconductive crystalline material (36) by heating with an energy beam (40), for example from an excimer laser. The use of an energy beam (40) permits easy localization of the heating (and consequent conversion) both vertically and laterally. The deposition (e.g. by plasma-enhanced chemical vapour deposition) and the beam annealing can both be carried out without heating the substrate (14) to high temperatures, and so a glass or other low-cost substrate (14) can be used. An unconverted part (32a) underlying the crystalline silicon body portion (36) can form at least part of a gate insulator of the TFT.
    Type: Grant
    Filed: June 15, 1994
    Date of Patent: November 14, 1995
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 5466618
    Abstract: A method for fabricating an LCD-TFT, which can prevent degradation of image quality of a liquid crystal display by preventing blackening of the pixel electrode due to H.sub.2 plasma at the time of deposition of a protective insulation film. The method includes the steps of forming a gate electrode on a transparent glass substrate, and forming a gate insulation film, a semiconductor layer, and an impurity doped semiconductor layer successively over the surface of the substrate. The semiconductor layer and the impurity doped semiconductor layer are patterned, leaving layers only over a part of the gate insulation film over the gate electrode. A pixel electrode is formed on a part of the gate insulation film offset from the gate electrode. A metal barrier layer and source/drain electrodes are over the surface of the substrate.
    Type: Grant
    Filed: December 29, 1994
    Date of Patent: November 14, 1995
    Assignee: Goldstar Co., Ltd.
    Inventor: Jin H. Kim
  • Patent number: 5466613
    Abstract: A camera device having favorable multiplication characteristics (quantum efficiency) as well as improved sensitivity in a visible light region (especially the region on the red side) and a method of manufacturing the same are provided. The camera device includes a hole injection stop layer, a first photoelectric converting layer including selenium, a second photoelectric converting layer having spectral sensitivity characteristics which are different from those of the first photoelectric converting layer, a third photoelectric converting layer including selenium, and an electron injection stop layer. As a result, it is possible to improve multiplication characteristics (quantum efficiency) and to improve the sensitivity in the visible light region (especially the region on the red side) simultaneously.
    Type: Grant
    Filed: January 10, 1995
    Date of Patent: November 14, 1995
    Assignees: Nippon Hoso Kyokai, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiko Andoh, Kazunori Miyakawa, Hidekazu Yamamoto, Masao Yamawaki
  • Patent number: 5466612
    Abstract: A dielectric film is formed on a P type silicon substrate. Then a specified resist pattern is formed on the dielectric film. Using this resist pattern as the mask, a phosphorus ion beam is implanted. Then, removing the resist pattern, heat treatment is given. By this heat treatment, a photo diode is formed in a depth of about 1 .mu.m. A specified resist pattern is formed again on the dielectric film. Using this resist pattern as the mask, boron ions are implanted. Thus, a channel stopper region is formed. Afterwards, removing the resist pattern, the dielectric film is removed. Again, a dielectric film is formed on the silicon substrate. Later, a stacked oxide film is formed in the other regions than the region for forming the photo diode on the dielectric film. Using the stacked oxide film as the mask, a boron ion beam is implanted.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: November 14, 1995
    Assignee: Matsushita Electronics Corp.
    Inventors: Genshu Fuse, Katuya Ishikawa
  • Patent number: 5466634
    Abstract: Methods of fabrication for electronic modules having electrically interconnected side and end surface metallization layers and associated electronic modules are set forth. The methods include providing a stack comprising a plurality of stacked IC chips. A side surface thin-film metallization layer is formed on the stack. Next, an end surface thin-film metallization layer is formed the stack such that the side surface and end surface thin-film metallization layers directly electrically interconnect. Alternatively, each IC chip of a stack may include an end surface metallization layer such that separate formation of an end surface metallization layer on an end surface of the stack is unnecessary. The methods also include forming an electronic module by first providing a long stack of IC chips, testing the chips of the stack, and then segmenting the long stack into multiple small stacks of functional IC chips based upon the test results.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Kenneth E. Beilstein, Jr., Claude L. Bertin, John E. Cronin, Wayne J. Howell, James M. Leas, Robert B. Phillips
  • Patent number: 5466620
    Abstract: A method for fabricating a TFT-LCD which enables point defects such as electrical short circuits between a pixel and a thin film transistor or between a bus line and a pixel to be repaired during fabrication.
    Type: Grant
    Filed: December 14, 1994
    Date of Patent: November 14, 1995
    Assignee: Goldstar Co., Ltd.
    Inventor: Young U. Bang
  • Patent number: 5466632
    Abstract: A method of forming field oxides with curvilinear boundaries between active regions on a substrate in an integrated circuit (IC) so that the stresses induced in the active regions due to the formation of field oxide can be reduced. Problems like junction leakage are reduced due to the rounded boundaries of the field oxides.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: November 14, 1995
    Assignee: United Microelectronics Corp.
    Inventors: Water Lur, Jiun Y. Wu
  • Patent number: 5464783
    Abstract: A method for making gate dielectrics for MOS devices includes first forming a silicon oxynitride layer, and then forming a silicon dioxide layer that underlies the oxynitride layer. The oxynitride layer functions as a membrane for controlled diffusion of oxygen to the oxidation region of the silicon substrate.
    Type: Grant
    Filed: February 2, 1995
    Date of Patent: November 7, 1995
    Assignee: AT&T Corp.
    Inventors: Young O. Kim, Lalita Manchanda, Gary R. Weber
  • Patent number: 5464453
    Abstract: The present invention relates to an improved method to produce an electrical storage device having useful characteristics such as higher charge density, small volume, long-term reliable charge/discharge cycles, low leakage current, and the like. The dry preunit has useful properties in that it can be stored for long periods prior to contact with a non-aqueous or aqueous electrolyte. When the electrode surfaces are contacted with a non-aqueous or aqueous electrolyte, the novel capacitors produced are useful as a portable power supply in applications such as in defibrillator, electrical vehicles, radiotelephones etc.
    Type: Grant
    Filed: September 18, 1992
    Date of Patent: November 7, 1995
    Assignee: Pinnacle Research Institute, Inc.
    Inventors: Robert R. Tong, James M. Poplett, Alan B. McEwen, Gary E. Mason, Mark L. Goodwin, K. C. Tsai, Ronald L. Anderson, James P. Nelson
  • Patent number: 5462893
    Abstract: An amorphous silicon layer is used as an etch stop and is formed on the side wall of a first wiring layer having a predetermined wiring width and formed in a predetermined shape by patterning. A silicon oxide layer is covering the first wiring layer and the amorphous silicon layer, and a through-hole is formed in the silicon oxide layer so that a portion of the first wiring layer is exposed. The width of the through-hole is equal to or larger than the wiring width of the first wiring layer. A tungsten layer is filling the through-hole, and a second wiring layer connected to the tungsten layer is formed on the silicon oxide layer.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: October 31, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumitomo Matsuoka, Naoki Ikeda
  • Patent number: 5462887
    Abstract: The process for making a matrix of thin layer transistors with memory capacitors includes forming a first conductive layer on a substrate, and in a first mask step, etching it to form row conductors of the matrix, gate contacts of the thin layer transistors and ground electrodes of the memory capacitors; forming a gate-insulating layer for the thin layer transistors; forming a semiconductor layer, especially an a-Si:H semiconductor layer; applying a p- or n-doped semiconductor layer to provide drain and source contacts; forming and etching a second conductive layer for the column conductors of the matrix of the thin layer transistors, the drain and source contacts of the thin layer transistors and the counter electrodes of the memory capacitors in a second mask step; plasma etching of the doped semiconductor layer with the second conductor layer acting as mask and determining an end of the etching process by observing the optical emission of an etching plasma used for the plasma etching; etching the undoped s
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: October 31, 1995
    Assignee: Ernst Luder
    Inventor: Joachim Gluck
  • Patent number: 5462885
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: October 31, 1995
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5462900
    Abstract: A method of manufacturing semiconductor elements with metal electrode films formed thereon in which the elements are spread on a metal screen having a mesh size small enough to prohibit the semiconductor elements from passing through it. The metal screen with the semiconductor elements on it is moved cyclically with a periodic motion substantially in a horizontal plane. As a result, burrs extending from the metal electrodes of the semiconductor elements are cut away or bent against the electrode surfaces of the semiconductor elements. The cyclic motion of the screen may be performed by tracing a figure-8 path.
    Type: Grant
    Filed: September 23, 1993
    Date of Patent: October 31, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Tetsuro Oki, Koichiro Harada, Ryuichi Neki, Kazuo Kawakami, Tsuyoshi Miyata, Kozo Matsuo
  • Patent number: 5460985
    Abstract: A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure.
    Type: Grant
    Filed: March 25, 1993
    Date of Patent: October 24, 1995
    Assignee: Ipics Corporation
    Inventors: Norihito Tokura, Shigeki Takahashi
  • Patent number: 5461011
    Abstract: A method of reflowing borophosphosilicate glass wherein wafers on a support that holds the wafers upright in spaced parallel relationship are introduced into a furnace. The wafers are heated to a temperature to achieve reflow while a main stream of heated inert gas is flowed over the wafers in a direction perpendicular to the planes of the substrates, while simultaneously an auxiliary stream of heated inert gas is flowed in a direction perpendicular to the main stream to prevent the formation of BPO.sub.4 crystals during reflow.
    Type: Grant
    Filed: August 12, 1994
    Date of Patent: October 24, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Chen-Chiu Hsue, Edward Houn
  • Patent number: 5459088
    Abstract: A method for making semiconductor thin film transistors (TFTs) having a bottom gate such that the gate electrode is formed of a polysilicon layer with a rugged surface, thereby providing a TFT which has a high on/off current ratio. According to the present invention, a thin film transistor may have a substrate; a gate electrode having a rugged surface formed on the substrate; a gate insulating layer formed on the gate electrode and the substrate; a semiconductor layer formed over the gate insulation layer; impurity regions formed at opposite sides of the gate electrode in the semiconductor layer. A method for making a thin film transistor according to present invention may include the steps of: forming a gate electrode having a rugged surface on a substrate; forming an insulating layer and a semiconductor layer on the substrate and the gate electrode; forming impurity regions at opposite sides of the gate electrode in the semiconductor layer.
    Type: Grant
    Filed: August 9, 1994
    Date of Patent: October 17, 1995
    Assignee: Goldstar Electron Co., Ltd.
    Inventors: Sa K. Rha, Youngil Cheon
  • Patent number: 5459099
    Abstract: A non-optical method for the formation of sub-half micron holes, vias, or trenches within a substrate. For example, a substrate having at least two buttresses or a trench having a interbuttress distance or a width of 1.0 to 0.5 microns, respectively, is conformally or non-conformally lined with a layer material. Thereafter, the layer material from horizontal surfaces is removed to expose the substrate underneath while leaving the layer material attached to the essentially vertical walls of the buttresses or the trenches essentially intact, thereby, narrowing the interbuttress distance or the trench width, respectively, to sub-half micron dimensions. The exposed substrate surface is then subjected to anisotropic etching to form sub-half micron trenches, holes or vias in the substrate. Finally, the buttresses and layer material are removed from the substrate.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: October 17, 1995
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: David S. Y. Hsu