Patents Examined by Brian R. Peugh
  • Patent number: 12079497
    Abstract: To quickly and appropriately adjust a performance of a storage system. A storage configuration optimization device for managing a storage system including one or more storages implemented by a plurality of SDS nodes includes a virtual CPU. The virtual CPU is configured to receive a request for an execution period and a necessary performance of a project using the storage system, and select, based on consumption information and performance information of a resource of the storage system, one or more change patterns satisfying the request for the execution period and the necessary performance from among a plurality of change patterns indicating configuration changes of the storage system.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: September 3, 2024
    Assignee: HITACHI, LTD.
    Inventors: Miho Kobayashi, Akira Deguchi, Kazuki Togo, Tsukasa Shibayama, Takanobu Suzuki
  • Patent number: 12079519
    Abstract: Techniques are provided for implementing a distributed control plane to facilitate communication between a container orchestration platform and a distributed storage architecture. The distributed storage architecture hosts worker nodes that manage distributed storage that can be made accessible to applications within the container orchestration platform through the distributed control plane. The distributed control plane includes control plane controllers that are each paired with a single worker node of the distributed storage architecture. The distributed control plane is configured to selectively route commands to control plane controllers that are paired with worker nodes that are current owners of objects targeted by the commands. If ownership of an object has changed from one worker node to another worker node, then subsequent commands will be re-routed to a control plane controller paired with the other worker node now owning the object.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: September 3, 2024
    Assignee: NetApp, Inc.
    Inventors: Praveen Kumar Hasti, Christopher Alan Busick
  • Patent number: 12067274
    Abstract: A method is provided. The method includes receiving a set of data blocks to be stored in a storage system. The storage system includes a plurality of non-volatile memory modules. The method also includes generating a set of segments based on the set of data blocks. A respective segment comprising portions of one or more erase blocks. The method further includes writing the set of segments to the non-volatile memory modules based on orderings of the portions of the one or more erase blocks.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 20, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Benjamin Scholbrock, Andrew R. Bernat, Ronald Karr, Xiaohui Wang
  • Patent number: 12061525
    Abstract: Techniques are provided for a snapshot difference interface integrated into an object store data management container. The snapshot difference interface is capable of interpreting an object format and snapshot file system format of snapshots backed up to an object store within objects formatted according to the object format. The snapshot difference interface can identify differences between snapshots, such as files that changed between the snapshots, while the snapshots are still resident within the object store. Because the snapshot difference interface does not retrieve the snapshots from the object store, security is improved, resource and network consumption is reduced, there is less of an impact upon client I/O processing, and a catalog of the snapshots can be more efficiently built and recovered in the event of corruption.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: August 13, 2024
    Assignee: NetApp, Inc.
    Inventors: Tijin George, Sharankumar Yelheri
  • Patent number: 12056396
    Abstract: An illustrative method includes a storage-aware serverless function management system receiving a request to execute a serverless function instance of a serverless function implemented in a serverless system, the serverless function instance associated with a component of a storage system, determining a portion of the component accessible to the serverless function instance based on a storage system policy associated with the storage system, and executing the serverless function instance using the portion of the component of the storage system.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: August 6, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Taher Vohra, Luis Pablo Pabón
  • Patent number: 12056362
    Abstract: Various implementations relate to receiving, by a non-volatile memory device from a host, a host command include device context information of non-volatile memory devices. The device context includes an address of a buffer of each non-volatile memory device. In response to receiving the host command, portions of host data are divided among the non-volatile memory devices. The non-volatile memory device sends to the host a transfer request indicating transfer of each portion of the host data to a respective one of the non-volatile memory devices. The non-volatile memory device sends to another non-volatile memory device a peer command based on the device context information.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: August 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Mohinder Saluja
  • Patent number: 12050530
    Abstract: A method for performing table management of a memory device in predetermined communications architecture with aid of system-region garbage collection (GC) and associated apparatus are provided. The method may include: utilizing the memory controller to perform a system-region GC procedure to manage at least one table regarding internal management of the memory device. The system-region GC procedure may include: reading a set of first table contents from a set of first table pages; and writing the set of first table contents into a set of first system-region-GC-processed table pages of the at least one table block, and writing a first RAID parity of the set of first table contents into a first parity page corresponding to the set of first system-region-GC-processed table pages in the at least one table block, in order to generate a first system-region-GC-processed table RAID protection group, for protecting the set of first system-region-GC-processed table pages.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: July 30, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chen-Yin Lin, Chih-Wei Hsiao
  • Patent number: 12050779
    Abstract: The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Qi Dong
  • Patent number: 12050797
    Abstract: An object of the invention is to optimize a storage cost for data. There is provided a storage system including a storage device, a memory, and a processor configured to control input and output of data to and from the storage device. The processor monitors a storage amount that is at least one of a write amount (a total amount of data received as a write target) and a physical use amount (a total amount of data physically stored in the storage device), and a read amount (a total amount of data that is read), and calculates a fee as a storage cost that is a cost related to use of the storage device in a target period, based on a storage amount and a read amount in the target period in accordance with a monitoring result.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hiroaki Akutsu, Takahiro Naruko, Akifumi Suzuki
  • Patent number: 12050799
    Abstract: A first compute server of a distributed cloud computing network executes an application that controls reading and writing access to associated persistent data. The first compute server performs a write operation to the persistent data on local storage, notifies a piece of code that controls outgoing messages from the application that the write operation is pending, and transmits write information for the write operation to a set of other compute servers. If an acknowledgement of the write information is received from a quorum of the other compute servers, the application notifies the piece of code that the write operation is confirmed. Periodically the write information is transmitted to an external storage system. If a confirmation that the write information has been written is received from the storage system, the first compute server transmits a write confirmation notice to the other compute servers, which can then delete the write information.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: July 30, 2024
    Assignee: CLOUDFLARE, INC.
    Inventors: Kenton Taylor Varda, Glen Patrick Maddern, Alex Dwane Robinson
  • Patent number: 12038848
    Abstract: This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: July 16, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventor: Zion Kwok
  • Patent number: 12026385
    Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
  • Patent number: 12019545
    Abstract: A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: June 25, 2024
    Assignee: SK HYNIX INC.
    Inventors: Sung Woo Hyun, Myoung Seo Kim, Jae Hoon Kim
  • Patent number: 12013782
    Abstract: A processor with protection of an isolated memory and protection method for the isolated memory accessible only by a trusted core are shown. A processor has a trusted core with a right to access an isolated memory planned on a system memory, a normal core prohibited from accessing the isolated memory, and a last-level cache shared by the trusted core and the normal core. The in-core cache structure of the normal core and the last-level cache are included in a hierarchical cache system. In response to a memory access request issued by the normal core, the hierarchical cache system determines whether the memory access request hits the isolated memory and, if yes, the hierarchical cache system rejects the memory access request.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: June 18, 2024
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Yingbing Guan, Junjie Zhang, Fangong Gong, Yanting Li, Yipu Liu
  • Patent number: 12013779
    Abstract: A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 18, 2024
    Assignee: Kioxia Corporation
    Inventor: Daisuke Hashimoto
  • Patent number: 12014087
    Abstract: A method for performing data management of a memory device with aid of targeted protection control and associated apparatus are provided. The method may include: receiving a first host command from a host device; sending a first operating command to a non-volatile (NV) memory to read first stored data from a first location within the NV memory; monitoring a read count of the first location to determine whether the read count of the first location reaches a read count threshold; monitoring at least one error bit count of other stored data of at least one other location within the NV memory to determine whether the at least one error bit count reaches an error bit count threshold; and starting a targeted protection procedure to process second stored data, for preventing the second stored data from being damaged by at least one reading behavior of the host device.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 18, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Patent number: 12014047
    Abstract: Systems, methods, and apparatus are disclosed for management of data storage with stream based compressibility. In an example, an orchestrator including a storage controller managing one or more storage nodes executes on one or more processors. The orchestrator receives compression ratio measurements associated with attempts to compress data from a plurality of applications running on a plurality of service guests. The orchestrator receives a request for storing a first data stream from a first application running in a first service guest. Based on a compression ratio of previously stored data associated with the first application being less than a threshold, the orchestrator assigns a first compressibility setting to the first data stream. The first compressibility setting causes a storage node to store the first data stream without attempting to compress the first data stream.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: June 18, 2024
    Assignee: Red Hat, Inc.
    Inventors: Gabriel Zvi BenHanokh, Orit Wasserman, Yehoshua Salomon
  • Patent number: 12001679
    Abstract: An apparatus comprises a processing device configured to detect an input-output (IO) pressure condition relating to at least one logical storage volume of a storage system, to receive IO operations directed to the at least one logical storage volume, to extract processing entity identifiers from respective ones of the received IO operations, and to perform IO throttling for the at least one logical storage volume based at least in part on the extracted processing entity identifiers. For example, a first group of one or more of the IO operations each having a first processing entity identifier may be subject to the IO throttling, while a second group of one or more of the IO operations each having a second processing entity identifier different than the first processing entity identifier is not subject to the IO throttling. Other differences in IO throttling can be implemented using the extracted processing entity identifiers.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Dell Products L.P.
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 11994989
    Abstract: Techniques for analyzing cache efficiencies in storage systems based on in-depth metrics instrumentation. The techniques include collecting metrics instrumentation data for each page of a specific type stored in a cache memory component of a storage system. The metrics instrumentation data for each page of a specific type includes a timestamp indicating when the page was stored in the cache, a timestamp indicating when the last cache hit occurred for the page, a current number of cache hits for the page, and an indication of the specific type of page. The techniques further include, based on the metrics instrumentation data, obtaining a plurality of metrics for each specific type of page stored in the cache. The techniques further include, based on the plurality of metrics and/or the metrics instrumentation data, performing a remedial action to improve performance of the cache memory component or provide more optimal use of memory resources.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: May 28, 2024
    Assignee: Dell Products L.P.
    Inventors: Vladimir Shveidel, Lior Kamran, Leron Fliess
  • Patent number: 11989419
    Abstract: The disclosure provides an approach for storage device write performance improvement in a remote computing environment. Embodiments include creating, on a remote device that is remote from a client device, a virtual storage device corresponding to a physical storage device physically connected to the client device. Embodiments include receiving, by a driver on the remote device, a request from an application on the remote device to perform a write operation with respect to the virtual storage device. Embodiments include sending, by the remote device, a write operation to the client device based on the request. Embodiments include prior to receiving a confirmation from the client device that the write operation was received or completed, sending, by the driver, to the application, a message indicating that the write operation is complete. Embodiments include receiving, by the driver, based on the message, an additional request to perform an additional write operation.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: May 21, 2024
    Assignee: VMware LLC
    Inventors: Weigang Huang, Yueting Zhang