Patents Examined by Brian R. Peugh
  • Patent number: 10838858
    Abstract: A controller comprising: a scheduling unit suitable for scheduling a garbage collection recovery operation to be performed in a runtime state after end of abnormal situation using first and second operation logs; a scanning unit suitable for scanning a destination block to detect one or more valid pages during the garbage collection recovery operation; and a map updating unit suitable for updating L2P mapping information of the detected valid pages, wherein the first operation log indicates a location of a valid page, into which source block data is most recently copied, in a destination block, and wherein the second operation log indicates a location of a valid page, L2P mapping information of which is most recently updated, in the destination block.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Joon-Mo Koo
  • Patent number: 10838861
    Abstract: A firmware attempts to allocate memory address resources, such as memory addresses in a PCI I/O and a PCI memory address space, to bus devices in a multi-processor computing system. If an out-of-resource (OOR) condition occurs during allocation of the memory address resources, memory address resources can be re-allocated from stacks that were successfully allocated requested resources to stacks that were not successfully allocated requested resources. Memory address resources can also, or alternately, be re-allocated from sockets that were successfully allocated requested resources to sockets that were not successfully allocated requested resources. If stack-level or socket-level readjustment of the memory address resource allocation fails, a base memory address of a configuration memory address space can be lowered, and the allocation can be retried.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: November 17, 2020
    Assignee: American Megatrends International, LLC
    Inventors: Manickavasakam Karpagavinayagam, Harikrishna Doppalapudi, Altaf Hussain, Purandhar Nallagatla
  • Patent number: 10831376
    Abstract: A flash-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A plurality of processors execute a plurality of kernels offloaded from the host. A memory system includes a first memory that is used to map a data section of each kernel to the flash memory. A supervisor processor maps a region of the first memory pointed by a data section of a first kernel to a region of the flash memory to allow first data to move between the region of the first memory and the region of the flash memory, based on a first message which is transferred in accordance with execution of the first kernel by a first processor among the plurality of processors. A network integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: November 10, 2020
    Assignees: MemRay Corporation, Yonsei University, University- Industry Foundation (UIF)
    Inventors: Myoungsoo Jung, Jie Zhang
  • Patent number: 10827424
    Abstract: The present disclosure relates to a mobile terminal in which a clock frequency of a memory varies as needed and a control method thereof, and the mobile terminal may include a memory provided with a table comprising information on a memory clock frequency corresponding to a different multiple of a preset source clock frequency, and a controller configured to primarily change the memory clock frequency of the mobile terminal to any one of frequencies according to the table in accordance with at least one of functions or applications carried out in the mobile terminal, wherein when the memory clock frequency is primarily changed, the controller secondarily changes the changed memory clock frequency to a frequency different from the changed memory clock frequency according to whether or not the communication performance of the mobile terminal is degraded.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Seungkeun Oh, Junsu Park, Jehyun Baek
  • Patent number: 10824559
    Abstract: A read request for a counter designated to be only cached in a global cache is received. The counter is excluded from being persisted in and retrieved from one or more primary data sources It is determined whether the counter has already been created in the global cache. If the counter has already been created in the global cache, the counter is created in the global cache with an initial counter value while continually excluding the counter from being persisted in and retrieved from the one or more primary data sources. The counter is cached with a time-to-live (TTL) time period. The time-to-live time period is to be renewed on each subsequent read request of the counter. The counter is temporally stored in the data object cache until the TTL time period lapses.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 3, 2020
    Assignee: salesforce.com, inc.
    Inventors: Sameer Khan, Sanjaya Lai
  • Patent number: 10817466
    Abstract: Aspects described herein may relate to a data processing engine that executes on a computing device in order to store data from one or more feed files, which may be heterogeneous, to a destination data structure on a designated computing device. Because the files may be huge in size, it is important that the files be stored in a manner in order to reduce the time to move the data and to support am efficient mechanism for recovering from errors. A feed file may be dynamically partitioned into groups of contiguous rows based on a dynamic partitioning key, where data chunks are loaded into a plurality of clone tables and subsequently moved into a destination data structure. The data processing engine may determine a row size for the clone files and request for resources from a computing cloud to obtain those resources.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Bank of America Corporation
    Inventors: Netla Hanumantha Reddy, Venugopala Rao Randhi, Vijaya Kumar Vegulla, Rama Venkata S. Kavali
  • Patent number: 10802976
    Abstract: Provided herein may be a storage device configured to perform a cache read operation by each memory device. The storage device may include a plurality of memory devices each including a plurality of memory blocks, and a memory controller configured to store and set cache setting information for each of the plurality of memory device, and control the plurality of memory devices such that, as a read operation on a select one of the plurality of memory devices, one of a cache read operation and a normal read operation is performed based on the cache setting information set for of the select memory device.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10802958
    Abstract: A storage device determines whether or not reading target data subjected to a first conversion process is divided and stored into multiple pages. When the data subjected to the first conversion process is stored in one of a plurality of pages, the data is read from the page, and a second conversion process for returning the data to a state before the data is subjected to the first conversion process is executed to the data. When the reading target data is divided and stored into two or more of the plurality of pages, a portion of the data is read from each of the two or more pages in which the portion of the data is stored, the portion of the data is stored in the buffer memory, the data subjected to the first conversion process is restored, and the second conversion process is executed to the restored data.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: October 13, 2020
    Assignee: HITACHI, LTD.
    Inventors: Hiroki Fujii, Hideyuki Koseki, Atsushi Kawamura
  • Patent number: 10802742
    Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Rezaul Haque, Lady Nataly Pinilla Pico
  • Patent number: 10802980
    Abstract: A computing device includes a volatile memory that includes a first cache, a non-volatile storage that includes a second cache, and a cache service. The cache service, responsive to a cache miss, retrieves that asset and writes that asset to the first cache and not the second cache. The cache service reads the asset from the first cache responsive to requests for the asset until the asset is evicted from the first cache or until the asset is promoted to the second cache. The cache service promotes the asset to the second cache upon determining that a set of one or more criteria are satisfied including a predefined number of cache hits for the asset when it is in the first cache. The cache service reads the asset from the second cache responsive to requests for the asset until the asset is evicted from the second cache.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 13, 2020
    Assignee: CLOUDFLARE, INC.
    Inventors: Samantha Aki Shugaeva, Ivan Babrou, Yuchen Wu
  • Patent number: 10795585
    Abstract: An embodiment of a semiconductor apparatus may include technology to determine if a memory operation on a memory is avoidable, and suppress the memory operation if the memory operation is determined to be avoidable. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Kshitij Doshi, Bhanu Shankar
  • Patent number: 10789007
    Abstract: A management device includes a processor that determines, upon receiving a request for deletion of a first volume set in a first storage area of a first storage device, whether a second volume different from the first volume is set in the first storage area. The processor detects, when it is determined that the second volume is set, a continuous empty area equal to or larger than the second volume from among storage areas of a second storage device. The processor causes the first storage device to perform the deletion of the first volume from the first storage area, evacuation of data of the second volume to the continuous empty area, and upon completion of the evacuation, migration of the second volume to a migration destination area within the first storage area from the second storage device.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 29, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuuichi Kobayashi, Keiji Miyauchi, Junichi Matsuda
  • Patent number: 10776280
    Abstract: A data storage device is provided. The data storage includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables, and includes a first logical unit number (LUN) and a second LUN that are respectively controlled by a first chip enable (CE) signal and a second CE signal. The memory controller receives a write command from a host, and forms super page data using logical pages of data in the write command. The memory controller reads one of the group-mapping tables from the first LUN or the second LUN to the DRAM after sequentially enabling the first CE signal and second CE signal to write a first portion and a second portion of the super page data to the first LUN and the second LUN.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 15, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Chen-Ning Yang, Chien-Chung Chung, Jian-Wei Sun
  • Patent number: 10768846
    Abstract: An information processing apparatus includes: a controller that controls a plurality of storage devices and transmits and receives data to and from the plurality of storage devices; and a bridge that communicates with the controller via a predetermined interface, communicates with each of the plurality of storage devices via each of a plurality of predetermined interfaces, and bridges the communications between the controller and the plurality of storage devices. The controller acquires information of a master boot record from each of the plurality of storage devices, and generates information of a master boot record in a virtual storage device to provide the plurality of storage devices as one storage device. The bridge controls a process for writing the information of the master boot record in the virtual storage device into a region of a master boot record in a first storage device out of the plurality of storage devices.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 8, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeshi Aoyagi
  • Patent number: 10761760
    Abstract: Disclosed herein are methods, systems, and processes to improve the duplication of data between disparate deduplication systems. Source fingerprints are generated for data blocks using a source fingerprint algorithm at a source deduplication system. The source fingerprints and previously-generated source fingerprints are used to determine whether the data blocks are new or modified. If the data blocks are new or modified, target fingerprints are generated for the data blocks using a target fingerprint algorithm associated with a target deduplication system. The target fingerprints are sent to the target deduplication system.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 1, 2020
    Assignee: Veritas Technologies LLC
    Inventor: Thomas G. Clifford
  • Patent number: 10754547
    Abstract: Disclosed is a method of managing a disaggregated memory. According to the present disclosure, the method includes: assigning at least one memory page to a local memory and a remote memory; checking a request for access to the memory page; checking whether a target performance ratio required in service is satisfied or not when the memory page requested to be accessed is assigned to the remote memory; predicting a size of the local memory on the basis of an LRU distance-based histogram when the target performance ratio is not satisfied; and reassigning the memory page requested to be accessed in consideration of the predicted size of the local memory.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 25, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kang Ho Kim, Kwang Won Koh
  • Patent number: 10754555
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Jeffrey Munsil, Jackson Ellis, Mark Ish
  • Patent number: 10747453
    Abstract: A method is disclosed for configuring a storage system, comprising: identifying at least one synchronous flow that is executed by the storage system, the synchronous flow being executed in response to a plurality of I/O requests that are received at the storage system; identifying a first synchronization object that is used by the synchronous flow, the first synchronization object being configured to control access to a first resource based on availability of one or more first credits for accessing the first resource; identifying at least one background flow that is configured to supply the first credits to the first synchronization object; detecting whether a first latency growth that is associated with the background flow corelates with a second latency growth that is associated with the storage system; and when the first latency growth correlates with the second latency growth, causing the storage system to increase a rate at Which the first credits are supplied to the first synchronization object by the b
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Kleiner, Vladimir Shveidel
  • Patent number: 10747472
    Abstract: Techniques perform operation control in a storage system. The techniques involve obtaining a performance parameter of the storage system. The performance parameter is associated with at least one of access response time and resource utilization of the storage system. The techniques further involve obtaining a target performance parameter. The target performance parameter indicates a desired value of the performance parameter. The techniques further involve: in response to the performance parameter exceeding a first threshold, determining a scheduling parameter based on the performance parameter and the target performance parameter. The scheduling parameter is used to control execution of background operations in the storage system. In accordance with at least some of the techniques, background operations in the storage system can be effectively controlled, so that the resource usage and input/output performance can be improved.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: August 18, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Shuo Lv, Ming Zhang
  • Patent number: 10740225
    Abstract: A radio communication processor receives first received data including first write data, a first address within a first area of a nonvolatile memory, and error detection information or second received data including second write data whose data amount is larger than a data amount of the first write data and a second address within a second area of the nonvolatile memory. If the radio communication processor receives the first received data, then a controller stores the first write data in a volatile buffer. If there is no error in the first write data, then the controller reads out the first write data from the volatile buffer and stores the first write data in the first area. If the radio communication processor receives the second received data, then the controller stores the second write data in the second area without storing the second write data in the volatile buffer.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 11, 2020
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Takahiko Sato