Patents Examined by Brian R. Peugh
  • Patent number: 10372366
    Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 6, 2019
    Assignee: VIOLIN SYSTEMS LLC
    Inventor: Jon C. R. Bennett
  • Patent number: 10365840
    Abstract: A network-attached storage system and method includes a network-attached storage apparatus and removable storage medium installed in sockets in that apparatus. The storage medium includes an RF receiver and circuitry for erasing or disabling access to memory thereon. A host controller determines when a removable storage medium has been installed in or removed from a socket. A network interface controller is provided for coupling to an external network. An RF transmitter is coupled to a controller. The controller is coupled to each socket via the host controller and to the network interface controller. The controller determines, based on signals from the host controller, when the removal of a removable storage medium from the socket is unauthorized and sends a signal to the RF transmitter for transmission to the RF receiver in the removed removable storage medium to cause the memory therein to be erased or access thereto to be disabled.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 30, 2019
    Assignee: The Boeing Company
    Inventors: Aaron N. Voigt, John M. Hood
  • Patent number: 10359967
    Abstract: A computer system includes a plurality of computer nodes communicating with each other via a network. Each of the plurality of computer nodes includes a local storage and at least one virtual machine. Each of the plurality of computer nodes transfers write data for the local storage to at least one different computer node for redundancy. A computer included in the computer system is configured to: obtain information indicating a write load amount of a first virtual machine; obtain information indicating remaining writable space of a local storage of a destination computer node among the plurality of computer nodes; and determine whether or not the first virtual machine should be transferred to the destination computer node, based on the write load amount of the first virtual machine and the remaining writable space of the destination computer node.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: July 23, 2019
    Assignee: HITACHI, LTD.
    Inventors: Hiroaki Akutsu, Akira Yamamoto, Takahiro Yamamoto, Yoshinori Ohira
  • Patent number: 10360154
    Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 23, 2019
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Sata Busayarat
  • Patent number: 10353626
    Abstract: A method of performing a write operation, the method comprising: comparing a data pattern of a currently received command directing a write operation to data patterns of at least one previously received command; and performing a write operation, based on the currently received command directing the write operation, by writing the data patterns of the at least one previously received command instead of the data pattern of the currently received command when the data pattern of the currently received command directing the write operation is identical to the data patterns of the at least one previously received command
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-uk Kim, Ayberk Ozturk, Dinne Girish, Richard Neil Deglin, Geun-soo Kim, Du-won Hong, Dong-hyuk Ihm
  • Patent number: 10353822
    Abstract: The described technology is directed towards efficiently invalidating cached data (e.g., expired data) in a hash-mapped cache, e.g., on a timed basis. As a result, data is able returned from the cache without checking for whether that data is expired, (if desired and acceptable), because if expired, the data is only briefly expired since the last invalidation run. To this end, a data structure such as a linked list is maintained to track information representative of hash-mapped cache locations of a hash-mapped cache, in which the information tracks a sequential order of entering data into each hash-mapped cache location. An invalidation run is performed on part of the hash mapped cache, including using the tracking information to invalidate a sequence of one or more cache locations, e.g., only the sequence of those locations that contain expired data.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 16, 2019
    Assignee: HOME BOX OFFICE, INC.
    Inventor: Sata Busayarat
  • Patent number: 10346077
    Abstract: In one embodiment, a computer-implemented method for performing deduplication in conjunction with random read and write operations across a namespace that is divided into a plurality of disjoint regions is disclosed. The method includes: maintaining a metadata structure for each of the plurality of disjoint regions via the respective region manager, each metadata structure comprising metadata indicating a physical storage location of one or more data chunks associated with the respective region; and performing a deduplicated write operation. The deduplicated write operation includes: determining whether the disjoint regions comprise a second data chunk identical in content to a first data chunk; and in response to determining one or more of the plurality of disjoint regions other than the first region includes the second data chunk, establishing a reference from the first data chunk to the second data chunk. Corresponding systems and computer program products are also disclosed.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Amit, Aviv Caro, David D. Chambliss, Joseph S. Glider, Chaim Koifman, Yosef Shatsky
  • Patent number: 10339051
    Abstract: A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 2, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Paul Dennis Stultz, James T Bodner, Kevin G Depew
  • Patent number: 10339064
    Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Blake, Timothy C. Bronson, Jason D. Kohl, Pak-Kin Mak, Vesselina K. Papazova
  • Patent number: 10338814
    Abstract: A mechanism for non-disruptive virtual tape libraries configuration. Specifically, the introduction of various additional computer processes permit the configuration of a virtual tape library without requiring the shutdown and re-initialization of the host application on which the virtual tape library resides.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 2, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Tolstoy, Karyn Kelley, Larry McCloskey, Igor Matveevskiy
  • Patent number: 10339011
    Abstract: A method and system for implementing data lossless synthetic full backups. Specifically, the method and system disclosed herein improves upon traditional synthetic full backup operations by considering all user-checkpoint branches, rather than just the active user-checkpoint branch, representing all chains of incremental changes to a virtual disk of a virtual machine. In considering all user-checkpoint branches, no data pertinent to users involved in the development of the non-active (or inactive) user-checkpoint branches is lost.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 2, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Aaditya Rakesh Bansal, Sunil Yadav, Suman Chandra Tokuri, Pradeep Anappa, Soumen Acharya, Sudha Vamanraj Hebsur
  • Patent number: 10331557
    Abstract: A firmware attempts to allocate memory address resources, such as memory addresses in a PCI I/O and a PCI memory address space, to bus devices in a multi-processor computing system. If an out-of-resource (OOR) condition occurs during allocation of the memory address resources, memory address resources can be re-allocated from stacks that were successfully allocated requested resources to stacks that were not successfully allocated requested resources. Memory address resources can also, or alternately, be re-allocated from sockets that were successfully allocated requested resources to sockets that were not successfully allocated requested resources. If stack-level or socket-level readjustment of the memory address resource allocation fails, a base memory address of a configuration memory address space can be lowered, and the allocation can be retried.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 25, 2019
    Assignee: American Megatrends International, LLC
    Inventors: Manickavasakam Karpagavinayagam, Harikrishna Doppalapudi, Altaf Hussain, Purandhar Nallagatla
  • Patent number: 10318203
    Abstract: Disclosed herein are methods, systems, and processes to improve the duplication of data between disparate deduplication systems. Source fingerprints are generated for data blocks using a source fingerprint algorithm at a source deduplication system. The source fingerprints and previously-generated source fingerprints are used to determine whether the data blocks are new or modified. If the data blocks are new or modified, target fingerprints are generated for the data blocks using a target fingerprint algorithm associated with a target deduplication system. The target fingerprints are sent to the target deduplication system.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: June 11, 2019
    Assignee: Veritas Technologies LLC
    Inventor: Thomas G. Clifford
  • Patent number: 10310984
    Abstract: A storage apparatus includes a first storage device and a second storage device, out of logical-physical translation information which associates a logical page and a physical page in the second storage device with each other. Non-compressed logical-physical translation information in the first storage device is assumed to constitute a first tier, compressed logical-physical translation information in the first storage device is assumed to constitute a second tier, and compressed logical-physical translation information in the second storage device is assumed to constitute a third tier. The storage apparatus includes tier management information for managing which logical page is included in logical-physical translation information of which of the first tier, the second tier, and the third tier.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 4, 2019
    Assignee: HITACHI, LTD.
    Inventor: Atsushi Kawamura
  • Patent number: 10303372
    Abstract: A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Sungyong Seo, Sun-Young Lim, Uksong Kang, Chankyung Kim, Duckhyun Chang, JinHyeok Choi
  • Patent number: 10296459
    Abstract: Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a requester socket, includes: receiving the RAO instruction from the requester CPU core, determining a home agent in a home socket for the addressed cache line, providing a request for ownership (RFO) of the addressed cache line to the home agent, waiting for the home agent to either invalidate and retrieve a latest copy of the addressed cache line from a cache, or to fetch the addressed cache line from memory, receiving an acknowledgement and the addressed cache line, executing the RAO instruction on the received cache line atomically, subsequently receiving multiple local RAO instructions to the addressed cache line from one or more requester CPU cores, and executing the multiple local RAO instructions on the received cache line independently of the home agent.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Doddaballapur N. Jayasimha, Samantika S. Sury, Christopher J. Hughes, Jonas Svennebring, Yen-Cheng Liu, Stephen R. Van Doren, David A. Koufaty
  • Patent number: 10296261
    Abstract: An electronic device includes an embedded storage device and an application processor. The embedded storage device is connected to directly communicate with a removable storage device which processes a packet having a first characteristic. The embedded storage device processes a packet having a second characteristic. The application processor is connected to directly communicate with the embedded storage device, but not directly connected to the removable storage device. The application processor processes a packet having a third characteristic. The embedded storage device compensates at least one of the first characteristic or the second characteristic, such that at least one of a first packet of the first characteristic received from the removable storage device or a second packet of the second characteristic in the embedded storage device is provided to the application processor according to the third characteristic.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Lee, Sungho Seo, Hyuntae Park, Hwaseok Oh, JinHyeok Choi
  • Patent number: 10296224
    Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Peng Li, William K. Lui, Sanjeev N. Trika
  • Patent number: 10282099
    Abstract: Intelligent snapshot tiering facilitates efficient management of snapshots and efficient restore of snapshots. For intelligent snapshot tiering, a storage appliance can limit cross-tier migration to invalidated data blocks of a snapshot instead of an entire snapshot. Based on a policy, a storage appliance can identify a snapshot to be migrated to another storage tier and then determine which data blocks are invalidated by an immediately succeeding snapshot. This would limit network bandwidth consumption to the invalidated data blocks and maintain the valid data blocks at the faster access storage tier since the more recent snapshots are more likely to be restored.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 7, 2019
    Assignee: NetApp, Inc.
    Inventors: Ajay Pratap Singh Kushwah, Ling Zheng, Sharad Jain
  • Patent number: 10275376
    Abstract: A method for implementing cross device redundancy schemes with a single commit by receiving, by a write page allocation unit, a request to allocate data grains; responsive to receiving the request, performing, by the write page allocation unit, an analysis of a predetermined data layout map associated with a grain memory to identify a memory segment; allocating, by the write page allocation unit, a number of data grains to the memory segment, while computing redundancy data associated with the number of data grains; storing the number of data grains and the redundancy data to the memory segment of the grain memory; determining, by the write page allocation unit, whether a storage threshold associated with the grain memory has been satisfied; and responsive to the storage threshold associated with the grain memory being satisfied, transmitting data grains and redundancy data stored in the memory segment to one or more storage devices.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: April 30, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ashwin Narasimha, Krishanth Skandakumaran, Vijay Karamcheti, Ashish Singhai