Patents Examined by Brian Sircus
  • Patent number: 7202637
    Abstract: The present invention provides an improved control method and apparatus allowing units arranged at different spaced apart locations to be controlled without the need for a high bandwidth link between the units and the controller. This allows a single controller to control a number of remotely located units.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: April 10, 2007
    Assignee: The Turbo Genset Company Limited
    Inventors: Tim Charles Green, Hassan Mansir, Milan Prodanovic
  • Patent number: 7203050
    Abstract: An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor is connected to the control end of the NPN Darlington circuit. The gate of NMOS transistor is connected to the output end of the NPN Darlington circuit.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 10, 2007
    Assignee: Mediatek Inc.
    Inventors: Tao Cheng, Ding-Jeng Yu
  • Patent number: 7199993
    Abstract: An ion-generating component has, on an insulating substrate, a ground electrode, a high-voltage electrode, an insulating film provided on the surface of the ground electrode, and a wire electrode. A cutout is formed by cutting out one side of the insulating substrate. The root of the wire electrode is soldered to the high-voltage electrode, and the leading end thereof is positioned near the cutout. The wire electrode is made of an ultrafine wire having a diameter of about 100 ?m or less, for example, a piano wire, a tungsten wire, a stainless wire, or a titanium wire.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: April 3, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinji Kato, Yoshihiro Sako
  • Patent number: 7196893
    Abstract: The anti-interference filter and lightning arrester device is equipped with two series-connected gas capsule diverters (6, 7). With the gas capsule diverters (6, 7) a switching configuration (9) is connected. This switching configuration (9) is implemented such that in the event of an interference, the gas capsule diverters (6, 7) can be reliably reset to the nonconducting state. This is even possible in the presence of a DC voltage and/or high-frequency signals.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: March 27, 2007
    Assignee: Huber & Suhner AG
    Inventor: Beat Herrmann
  • Patent number: 7196889
    Abstract: An overvoltage protection device is formed in a semiconductor substrate having a plurality of doped regions for forming semiconductor devices. The overvoltage protection device is adapted to draw current away from a device to be protected from excess voltage and has a switchable device having a terminal adapted to be coupled to a potential source of excess voltage and to the semiconductor substrate for drawing current away from the potential source of excess voltage when the switchable device is triggered, and for directing the current to the semiconductor substrate. A Zener diode is coupled to a second terminal of the switchable device to trigger the switchable device to a conducting state. The Zener diode is formed in the same doped region of the substrate as the trigger of the switchable device.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: March 27, 2007
    Assignee: Medtronic, Inc.
    Inventors: Paul F Gerrish, Tyler J Mueller, Andreas A. Fenner, Mark Blanchfield
  • Patent number: 7196890
    Abstract: Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated circuit. The timing circuit has an RC node used for triggering a series of inverters configured to control an ESD dissipation device operably coupled to the high supply side node and the low side supply node of the circuit. A feedback transistor network and a feedback conditioning network is provided for ensuring that the ESD device is held on during an ESD event.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: March 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Jeremy Charles Smith
  • Patent number: 7196886
    Abstract: A resettable circuit interrupting device having a switch and timer circuit connected to the line side of the interrupting device to cause a leakage current to flow for a defined interval of time when power is applied. The timer and switch circuit comprises a timer powered by current from the phase leg of the device which is designed to operate for a defined interval of time. The timer starts operating when power is applied to the circuit interrupting device and normally continues to operate for the defined interval to time. Upon completion of the timed interval, the timer turns itself off and stays off until power is again applied to the device after an interruption. When power is first applied to the interrupting device, the timer is energized from the phase leg and causes the switch to close which connects the neutral leg on the line side of the interrupting device to a ground terminal.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: March 27, 2007
    Assignee: Leviton Manufacturing Co., Ltd.
    Inventors: David Chan, Steve Campolo
  • Patent number: 7196433
    Abstract: A multi-output circuit device with preset power supply priority that provides higher safety, wherein, the load of inferior priority depending on the preset overload breaking sequence is cut off first when the total load amperage exceeds the rated amperage while maintaining power supply to the load of superior priority under the operation status of variable local loads.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: March 27, 2007
    Inventor: Tai-Her Yang
  • Patent number: 7196891
    Abstract: A control circuit for a frequency converter is provided. The control circuit includes a switch circuit, a timer switch, a starter circuit, a starter relay, and a timer relay. The control circuit is capable of keeping the frequency converter on for a predetermined time period when the voltage level of the power supply is below a predetermined voltage level in order to keep the equipment operating. After the lapse of the predetermined period, if the voltage level is still below the predetermined voltage level, the circuit stops to the operation of the equipment to protect the equipment.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: March 27, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Chieh Chang, Lyman Tseng
  • Patent number: 7193336
    Abstract: A method and apparatus for reducing conductive thermal losses in high-current cryogenic power electronics systems needing large cables to interface between warm and cold environments. Thermal losses increase with increasing cross-sectional area. The total current at the warm/cold interface is split into many smaller currents by splitting the power buss into a plurality of parallel leads. Respective physical switches in each smaller lead at the interface interrupt current flow, and at the same time open the path for thermal conduction along the lead. When little or no current is flowing through the system, selected smaller leads of the power buss are physically opened by the associated switches to stop the thermal and electrical flow along these leads. Current diverts to another parallel lead in the buss but the cross section for heat flow is reduced at the interface.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: March 20, 2007
    Inventors: Otward M. Mueller, Michael J. Hennessy
  • Patent number: 7193337
    Abstract: A solid state power controller (SSPC) (100) includes a power switching controller (30) and power switching devices (PSDs) (20A, 20B, 20C) for controlling each phase of a multiple-phase load to switch-on or -off at a zero-crossing point of a corresponding phase of a multiple-phase power source. The power switching controller (30) may include an ASIC (25A, 25B, 25C) for controlling each PSD (20A, 20B, 20C) to switch the corresponding load phase on or off. The ASIC (25A, 25B, 25C) may be configured to control the PSD (20A, 20B, 20C) to switch-on the load phase at a detected zero-crossing point of the voltage supplied by the corresponding phase of the power source, and to switch-off the load phase at a detected zero-crossing point of the load current supplied by the corresponding phase of the power source.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: March 20, 2007
    Assignee: Honeywell International Inc.
    Inventor: That Nguyen
  • Patent number: 7192513
    Abstract: A cathodic protection junction box current equalizer has a plurality of output terminals each being connectable through a variable resistors to an anode, the resistors being controlled such that the corresponding anode outputs a desired current.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: March 20, 2007
    Assignee: Saudi Arabian Oil Company
    Inventor: Husain M. Al-Mahrous
  • Patent number: 7191863
    Abstract: An apparatus for preventing an erroneous operation of an electro-motion pedal device in an automobile and methods of use thereof, wherein an engine starting condition, positions of a shift lever and a parking brake activated condition are detected. When a safe condition of a non-moving automobile is detected, power is transmitted to an electro-motion pedal device to allow the pedal to be electronically adjusted, such that an erroneous operation of an electro-motion pedal device that might occur during an automobile in operation can be prevented to thereby avoid an accident in advance.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: March 20, 2007
    Assignee: Hyundai Motor Company
    Inventor: Kil-Jae Ahn
  • Patent number: 7193338
    Abstract: A method of tapping a high voltage transmission line for input into a power distribution substation is disclosed. The method comprises the steps of dividing the transmission line and attaching the conductors to the primaries of at least two transformers via a series connected first disconnect switch, second disconnect switch and circuit breaker. A bus interconnects the first disconnect switch and the second disconnect switch and the bus of the first transformer bay is connected to the bus of the second transformer bay using a circuit breaker. A system for the conversion of tapped high voltage electricity to medium voltage electricity is also disclosed.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: March 20, 2007
    Inventor: Gamal A. Ghali
  • Patent number: 7193830
    Abstract: The invention relates to surge suppressors. One embodiment provides a surge suppressing device including: a power circuit having an MOV and a thermal fuse in proximity to the MOV; an isolation structure containing the MOV and the thermal fuse; and a plurality of utility outlets in electrical communication with the power circuit. The isolation structure isolates the MOV and thermal fuse from at least a portion of the surge-suppressing device and encapsulates emissions from the MOV during an overvoltage event. Another embodiment provides a surge suppressing device including: a power section having a power circuit; an intermediate section adjacent to the power section; and an outlet section adjacent to the intermediate section such that the intermediate section separates the power section and the outlet section. The outlet section includes a plurality of utility outlets in electrical communication with the power circuit. Further embodiments are described.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: March 20, 2007
    Assignee: American Power Conversion Corporation
    Inventors: Greg Fournier, Mark H. Germagian, Ronnie L. Bell
  • Patent number: 7193335
    Abstract: A socket assembly enables a number of electrical appliances to be automatically isolated from, and reconnected to, an electrical power supply upon respectively switching off or on a “master” appliance. Generally, the assembly includes: a master electrical outlet and at least one slave electrical outlet, both connectable to a common power source; sensing means for sensing power drawn from the master electrical outlet; a controller operable to isolate the at least one slave electrical outlet from the power source when the sensing means detects a fall in power drawn from the master electrical outlet from a first, higher level to a second, lower level.
    Type: Grant
    Filed: November 11, 2002
    Date of Patent: March 20, 2007
    Assignee: One Click (IP) Limited
    Inventors: Norman Palmer, Peter Steven Robertson, Ian Browne
  • Patent number: 7193837
    Abstract: A plug includes an element that is electrically connected to a ground element in a receptacle in a set up configuration and an electrical connection that is attached to an element to be grounded whereby an element, person, or device, or the like, can be securely grounded using the ground circuit in a receptacle. Grounding is via a suitable signal circuit in one form of the invention.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: March 20, 2007
    Inventor: Barry M. Epstein
  • Patent number: 7190091
    Abstract: A selectable source input power supply is disclosed. According to one embodiment, a power supply is provided comprising an input stage including an input connector to couple the power supply to either of an AC input voltage or a DC input voltage, and an actuatable input switch to determine which of the AC input voltage and the DC input voltage is coupled to the power supply, to couple the input stage to an alternating current path in response to a determination that the AC input voltage is coupled to the power supply, and to couple the input stage to a direct current path in response to a determination that the DC input voltage is coupled to the power supply.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: March 13, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Robert A. Marshall
  • Patent number: 7190563
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a circuit from an ESD event, the ESD protection circuit comprises a metal-oxide semiconductor (MOS) device including a gate terminal, a first source/drain terminal, a second source/drain terminal and a bulk terminal, the bulk and first source/drain terminals being operatively coupled across the circuit to be protected, the gate and second source/drain terminals being coupled together; and a voltage generation circuit coupled between the bulk and gate terminals of the MOS device. The voltage generation circuit is configured to generate a voltage difference between the bulk and gate terminals of the MOS device during at least a portion of the ESD event. In this manner, a current handling capability of the MOS device is increased, thereby advantageously enabling a smaller sized device having a significantly smaller capacitance associated therewith to be employed in the ESD protection circuit.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: March 13, 2007
    Assignee: Agere Systems Inc.
    Inventor: Muhammed Ayman Shibib
  • Patent number: 7187527
    Abstract: A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: March 6, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Shin Su, Chun-Hsiang Lai, Cha-Ling Lu, Yen-Hung Yeh, Tao-Cheng Lu