Patents Examined by Brian T Misiura
  • Patent number: 11182309
    Abstract: Fabric Attached Memory (FAM) provides a pool of memory that can be accessed by one or more processors, such as a graphics processing unit(s) (GPU)(s), over a network fabric. In one instance, a technique is disclosed for using imperfect processors as memory controllers to allow memory, which is local to the imperfect processors, to be accessed by other processors as fabric attached memory. In another instance, memory address compaction is used within the fabric elements to fully utilize the available memory space.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: November 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: John Feehrer, Denis Foley, Mark Hummel, Vyas Venkataraman, Ram Gummadi, Samuel H. Duncan, Glenn Dearth, Brian Kelleher
  • Patent number: 11175689
    Abstract: A communication system including a physical layer circuit, a timer circuit, and a turnaround controller. The physical layer circuit provides an early turnaround indication upon detection of a turnaround command and before completion of the turnaround command. The timer circuit is programmed with a timeout value indicative of a maximum time of a turnaround procedure initiated by the turnaround command. The turnaround controller starts the timer circuit in response to the early turnaround indication. A transmit controller may begin retrieving information to transmit from a memory in response to the early turnaround indication, and may begin transmitting the retrieved information if the turnaround procedure completes before timeout of the timer circuit. The retrieved information may be configuration information for a sensor. The turnaround controller provides an error indication if the timer circuit times out indicating a turnaround error. The error indication enables remedial action to be taken.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Maik Brett, Naveen Kumar Jain, Shreya Singh, Anshul Goel
  • Patent number: 11169941
    Abstract: A host device comprises a processor coupled to a memory. The host device is configured to obtain from a storage system connectivity information characterizing one or more ports of the storage system, and to automatically establish connectivity of a particular type between the host device and one or more logical storage devices of the storage system based at least in part on the obtained connectivity information. For example, the host device can obtain the connectivity information directly from the storage system or via at least one intermediary device such as a management station. In some embodiments, the obtaining and automatically establishing are performed by at least one multi-path input-output driver of a multi-path layer of the host device. The connectivity of a particular type illustratively comprises Internet Small Computer System Interface (iSCSI) connectivity between the host device and the storage system, although other connectivity types can be supported.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: November 9, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinay G. Rao, Sanjib Mallick, Owen Crowley, Peniel Charles, Erik P. Smith, Arieh Don
  • Patent number: 11169948
    Abstract: A method includes detecting, by a first LVDC affiliated with a first host device, a request for a one-to-one communication with a second LVDC affiliated with a second host device, where data is conveyed between the LVDCs by varying loading on a bus at a frequency. The method further includes determining a desired number of channels to support the one-to-one communication based on one or more of: the first host device, the second host device, and information contained in the request, wherein the channels correspond to frequencies in a frequency band. The method further includes determining whether the desired number of channels is available for the one-to-one communication. When the desired number of channels is available for the one-to-one communication, allocating them for the one-to-one communication.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 9, 2021
    Assignee: SIGMASENSE, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11163583
    Abstract: An electronic device according to various embodiments includes: a connector configured to be connected with an external electronic device; a memory configured to store instructions; and a processor configured to execute the stored instructions to control the electronic device to identify a control signal received through a channel initially activated based on the external electronic device being connected to the connector from among a plurality of channels, and to perform control based on a message included in the identified control signal.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wookwang Lee, Guneet Singh Khurana, Dmitriy Moskvitin
  • Patent number: 11150722
    Abstract: Systems, methods, and computer-readable media are disclosed for mitigating thermal increases in electronic devices. Example devices may include memory and at least one processor configured to access the memory and execute computer-executable instructions to determine that a temperature of the device satisfies a first threshold, send a notification to an access point communicatively coupled to the device indicating that the device will enter a sleep state for a length of time, and cause the device to enter the sleep state. Certain embodiments may be configured to cause the device to enter an awake state after the length of time, determine that the temperature satisfies a second threshold, and determine that a period of time has elapsed. Some embodiments may be configured to determine that a first bandwidth mode is active at the device, and cause a second bandwidth mode to be activated at the device.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 19, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Ravi Ichapurapu, Sameet Ramakrishnan
  • Patent number: 11144088
    Abstract: Method and apparatus associated with clocking synchronization are disclosed herein. In various embodiment, a method for communication comprises: entering a clock training period, on successful performance of clock training handshake; entering a start static phase measurement (SSPM) sequence of clock training period, receiving a recovered clock; and processing the recovered clock to determine parts-per-million (PPM) differences, to be subsequently applied to compensate for the PPM differences determined during subsequent clocking synchronization. Linking training is performed after the subsequent clocking synchronization. In various embodiments, clocking synchronization comprises SSC synchronization. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Jagannadha Rao V. V. V. Rapeta, Mikal Hunsaker, Ronald Swartz, Robert Fulton, L. Mark Elzinga, Young Min Park, David R. Mulvihill
  • Patent number: 11146074
    Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yu Kinoshita
  • Patent number: 11137818
    Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 5, 2021
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Douglas S. Winterberg
  • Patent number: 11132314
    Abstract: An information handling system includes a device, a processor, and a runtime agent. the device provides a System Management Interrupt (SMI) in response to an error on the device. The processor receives the SMI, enters a System Management Mode (SMM), and executes first interrupt handler code in SMM to provide interrupt information associated with the SMI when the SMI is associated with a non-critical error on the device, and exit SMM to a runtime mode. The runtime agent receives the interrupt information during the runtime mode to execute second interrupt handler code to service the non-critical error on the device.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Dell Products L.P.
    Inventors: Akkiah Maddukuri, Arun Muthaiyan, Jordan Chin, Timothy M. Lambert, Nasiha Hrustemovic
  • Patent number: 11126218
    Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 21, 2021
    Assignee: Integrated Device Technology, Inc.
    Inventors: Zaher Baidas, Ernst JG den Broeder, Leonid Goldin
  • Patent number: 11122506
    Abstract: Methods, apparatus, and computer-readable media are described to encode, by a first station (STA), a polling signal for periodic transmission to a second STA during each air activity instance of a plurality of air activity instances. The first STA detects an interface between a MAC layer and a software stack of a communication protocol is in a low-power state. The communication protocol is associated with a communication link between the first STA and the second STA. An empty packet from the second STA is decoded. The empty packet is received in response to the polling signal transmitted during an air activity instance of the plurality of air activity instances. The periodicity of the periodic transmission of the polling signal is adjusted based on the detected low-power state and the decoded empty packet.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Sunil Kumar, Hakan Magnus Eriksson, Sebastien Fievet, Oren Haggai, Izoslav Tchigevsky, Udi Shtalrid
  • Patent number: 11093278
    Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 17, 2021
    Assignee: INTEL CORPORATION
    Inventors: Michael Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jeremy Shrall
  • Patent number: 11093428
    Abstract: A convertible I/O signal processor is convertible between different operating configurations for connecting multiple field devices to the I/O signal processor by selectable types of electrical connectors such as cables, terminal blocks, and the like. The I/O signal processor includes a signal processing module connected to a signal processor and an interface module removably connected to the signal processing module. The interface module includes electrical connectors for receiving/transmitting I/O signals from and to field devices. The interface module and the signal processing module define I/O channels extending between the electrical connectors and the signal processor. The interface module in embodiments includes I/O module connectors that enable removable I/O modules to be interposed in the I/O channels.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: August 17, 2021
    Assignee: Phoenix Contact Development and Manufacturing, Inc.
    Inventors: Brian John Gillespie, Davis Mathews
  • Patent number: 11086799
    Abstract: A method for configuring a controller in a master control chip can include operations such as: a controller is configured according to a sampling rate, a bit width occupied by data transmission of at least one peripheral and the number of the at least one peripheral plugged into an interface corresponding to the controller; and data transmitted by the at least one peripheral plugged into the interface is received through the configured controller. A configuration parameter of the controller is reconfigured, and then the peripheral may be connected to the interface at timing generated by the controller and the data transmitted by the at least one peripheral is acquired, thereby increasing the types of peripherals supported by the master control chip, and increasing the number of peripherals that can be plugged into the master control chip.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 10, 2021
    Assignee: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.
    Inventor: Tao Jin
  • Patent number: 11082544
    Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 3, 2021
    Assignee: Microchip Technology Incorporated
    Inventor: Jason Sachs
  • Patent number: 11079827
    Abstract: Provided are embodiments for performing a cognitive state of charge recalibration, where the embodiments include determining a device usage schedule for a device, and determining a threshold time for performing a recalibration function of a battery of the device. In addition, the embodiments include identifying an available period in the device usage schedule based on the threshold time to perform the recalibration function, and updating device calibration setting based on results of the recalibration function.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John S. Werner, Noah Singer, John Torok, Arkadiy O. Tsfasman, Budy Notohardjono
  • Patent number: 11074206
    Abstract: The present disclosure advantageously provides a method and system for transferring data over at least one interconnect. A request node, coupled to an interconnect, receives a first write burst from a first device over a first connection, divides the first write burst into an ordered sequence of smaller write requests based on the size of the first write burst, and sends the ordered sequence of write requests to a home node coupled to the interconnect. The home node generates an ordered sequence of write transactions based on the ordered sequence of write requests, and sends the ordered sequence of write transactions to a write combiner coupled to the home node. The write combiner combines the ordered sequence of write transactions into a second write burst that is the same size as the first write burst, and sends the second write burst to a second device over a second connection.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: July 27, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Tushar P Ringe, Kishore Kumar Jagadeesha, Ashok Kumar Tummala, Rishabh Jain, Devi Sravanthi Yalamarthy
  • Patent number: 11068422
    Abstract: Described herein are embodiments that adaptively reduce the number of interrupts that occur between a device controller and a computer system. Device commands are submitted to the controller by an operating system on behalf of an application. The device performs the received commands and indicates command completions to the controller. A counter counts completions, and if the count exceeds a threshold number, the controller generates an interrupt to the computer system. If the count is greater than zero and the timeout interval has expired, then the controller generates an interrupt to the computer system. In some embodiments, the application attaches flags to one of the commands indicating that an interrupt relating to completion of the flagged command should be generated as soon as possible or that an interrupt relating to completion of all commands prior to and including the flagged command should be generated as soon as possible.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: July 20, 2021
    Assignee: VMware, Inc.
    Inventors: Amy Tai, Igor Smolyar, Dan Tsafrir, Michael Wei, Nadav Amit
  • Patent number: 11061464
    Abstract: An electronic device includes a key circuit, a first universal serial bus (USB) circuit coupled to the key circuit, where the key circuit outputs different signals when different keys on the key circuit are pressed. The first USB circuit is configured for USB communication, and a first power delivery (PD) circuit is coupled to the key circuit and configured to convert a signal output by the key circuit into a PD signal and transmit the PD signal to a second electronic device to enable the second electronic device to process the key operation when the first USB circuit is in a power-off state and a key operation is performed on the key circuit.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 13, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Renjun Dai