Patents Examined by Brian T Misiura
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Patent number: 11741025Abstract: A storage system and method for providing a dual-priority credit system are disclosed. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive, from a host, a plurality of credits for sending messages to the host; allocate a first portion of the plurality of credits for non-urgent messages; and allocate a second portion of the plurality of credits for urgent messages. Other embodiments are provided.Type: GrantFiled: February 18, 2021Date of Patent: August 29, 2023Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Ariel Navon, Judah Gamliel Hahn, Alon Marcu
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Patent number: 11740910Abstract: An indication that a virtual machine is starting is received. Requested data blocks associated with the virtual machine are identified. Based on identifiers of the requested data blocks, a trained learning model is used to predict one or more subsequent data blocks likely to be requested while the virtual machine is starting. The one or more subsequent data blocks are caused to be preloaded in a cache storage.Type: GrantFiled: September 21, 2022Date of Patent: August 29, 2023Assignee: Cohesity, Inc.Inventors: Ayushi Jain, Vedant
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Patent number: 11733765Abstract: Control device for a power over Ethernet system having multiple power source devices comprises plural control circuits and a signal bus connecting them. Each control device connects plural power source devices and plural port switches, which controls power supply to a port to be connected by a power consuming device. Detection circuit detects at least one power supply state combination. Control signal generator picks up a power control combination signal corresponding to a detected power supply state combination from a power supply to power control look-up-table, upon change in the power supply state and provides the power control signals to corresponding port switches.Type: GrantFiled: July 7, 2021Date of Patent: August 22, 2023Assignee: IC PLUS CORP.Inventor: Chuan Ching Yu
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Patent number: 11726942Abstract: Disclosed are a module assembly and a multi-master communication method thereof, and more particularly, a module assembly including a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, in which at least one module requiring the data transmission among the plurality of modules performs first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, at least one module performing the first declaration for the transmission intention performs second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation.Type: GrantFiled: December 16, 2021Date of Patent: August 15, 2023Assignee: LUXROBO CO., LTD.Inventors: Gibag Yi, Seungbae Son
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Patent number: 11726937Abstract: A method for controlling the sending of data by a plurality of processors belonging to a device, the method comprising: sending a first message to a first processor of the plurality of processors to grant permission to the first processor of the plurality of processors to send a first set of data packets over at least one external interface of the device; receiving from the first processor, an identifier of a second processor of the plurality of processors; and in response to receipt of the identifier of the second processor, send a second message to the second processor to grant permission to the second processor to send a second set of data packets over the at least one external interface.Type: GrantFiled: September 16, 2021Date of Patent: August 15, 2023Assignee: GRAPHCORE LIMITEDInventors: Graham Bernard Cunningham, Stephen Felix
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Patent number: 11714762Abstract: An arbitration control circuit in a pseudo-static random access memory (PSRAM) device includes a first arbiter circuit and a second arbiter circuit. The first arbiter circuit receives a normal access request signal and a refresh access request signal and generates a first output signal in response to a logical operation to arbitrate between the normal access reqeuest signal and the refresh access request signal. The second arbiter circuit configured to receive the first output signal and a delayed signal of the first output signal, and to generate a second output signal in response to a logical operation of the first output signal and the delayed signal. The second output signal has a first logical state indicative of granting the read or write access request and a second logical state indicative of granting the refresh access request to the memory cells of the PSRAM device.Type: GrantFiled: August 1, 2022Date of Patent: August 1, 2023Assignee: Integrated Silicon Solution, (Cayman) Inc.Inventors: Geun-Young Park, Seong-Jun Jang
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Patent number: 11704270Abstract: A network comprising interconnected first and second processors, each processor comprising one or more of: multiple processing units arranged on a chip configured to execute program code; an on-chip interconnect comprising groups of exchange paths connected to receive data from corresponding groups of the processing units; external interfaces configured to communicate data off-chip as packets, each having a destination address, external interfaces of the first and second processors being connected by an external link; multiple exchange blocks, each connected to groups of the exchange paths; a routing bus configured to route packets between the exchange blocks and the external interfaces. Processing units of the first processor generate off-chip packets such that the group of processing units serviced by the first exchange block on the first processor address off-chip packets to the group of processing units on the second processor serviced by the corresponding first exchange block of the second processor.Type: GrantFiled: July 13, 2021Date of Patent: July 18, 2023Assignee: GRAPHCORE LIMITEDInventors: Simon Knowles, Hachem Yassine
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Patent number: 11704276Abstract: A method includes receiving a chip select signal at an SPI client device. The method also includes, responsive to receiving the chip select signal, transmitting a first bit of an SPI transmission to an SPI host device, where the first bit of the SPI transmission is transmitted with a delay based at least in part on a loop propagation delay of an SPI channel. The method includes receiving a clock signal at the SPI client device. The method also includes, responsive to receiving the clock signal, transmitting a second bit of the SPI transmission to the SPI host device.Type: GrantFiled: May 19, 2022Date of Patent: July 18, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Kristen N. Mogensen, Matthieu Chevrier, Martin Staebler
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Patent number: 11698874Abstract: Systems and methods enable data collection and analytics consumption with a generalized assurance framework using a message bus that supports a publish-subscribe model. A producer network element subscribes to a request topic on the message bus and posts, to the message bus, an announcement indicating a data topic is available from the producer network element. The producer network element receives via the message bus, the request topic including a request for the data topic and posts, to the message bus, records for the data topic in response to the request.Type: GrantFiled: February 9, 2022Date of Patent: July 11, 2023Assignee: Verizon Patent and Licensing Inc.Inventor: Kristen Sydney Young
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Patent number: 11693799Abstract: Bandwidth control can be provided for input/output channels according to some aspects described herein. In one example, a system can detect an input/output (I/O) request transmitted by a software application. In response to detecting the I/O request, the system can determine a bandwidth group that corresponds to an I/O channel associated with the I/O request. The system can then determine whether bandwidth consumption of the bandwidth group exceeds a predefined bandwidth limit. If so, the system can execute a predefined policy assigned to the I/O channel for handling the I/O request.Type: GrantFiled: September 20, 2021Date of Patent: July 4, 2023Assignee: RED HAT, INC.Inventors: David Butenhof, Lennart Poettering, Peter Portante, W Webb Scales
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Patent number: 11693796Abstract: Various implementations described herein are directed to a device having a multi-layered logic structure with a first logic layer and a second logic layer arranged vertically in a stacked configuration. The device may have a memory array that provides data, and also, the device may have an inter-layer data bus that vertically couples the memory array to the multi-layered logic structure. The inter-layer data bus may provide multiple data paths to the first logic layer and the second logic layer for reuse of the data provided by the memory array.Type: GrantFiled: May 31, 2021Date of Patent: July 4, 2023Assignee: Arm LimitedInventors: Paul Nicholas Whatmough, Zhi-Gang Liu, Supreet Jeloka, Saurabh Pijuskumar Sinha, Matthew Mattina
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Patent number: 11687479Abstract: Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.Type: GrantFiled: September 23, 2021Date of Patent: June 27, 2023Assignee: International Business Machines CorporationInventors: Jie Zheng, Deanna Postles Dunn Berger, Chad G. Wilson, Poornima P Sulibele, James Franklin Driftmyer
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Patent number: 11681642Abstract: A device comprising: a control bus; a plurality of requesting circuits each accessible on the control bus, wherein each of the plurality of requesting circuits is operable to dispatch read or write requests to the control bus for delivery to at least one of a plurality of receiving circuits, and the plurality of receiving circuits each accessible on the control bus, and each of which is operable to receive requests from the at least one control bus and service the requests by providing at least one of read or write access to storage associated with the respective receiving circuit, wherein the control bus provides a ring path configured to support, the requests in circulation in the ring path, wherein the control bus is configured to propagate each of at least some of the requests at least until those requests have been serviced by at least one of the receiving circuits.Type: GrantFiled: May 24, 2021Date of Patent: June 20, 2023Assignee: GRAPHCORE LIMITEDInventors: Graham Bernard Cunningham, Daniel John Pelham Wilkinson
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Patent number: 11675733Abstract: Techniques for transmitting data include identifying data to be transmitted, adding the data to a queue, and in response to a data session window being open: extracting the data from the queue; transmitting the extracted data to a transceiver via a transmitter; monitoring an amount of data in the queue and determining that the transmitter has transmitted the extracted data to the transceiver; and in response, instructing the transceiver to end the data session window early and transition to a lower power state.Type: GrantFiled: June 15, 2021Date of Patent: June 13, 2023Assignee: ITRON, INC.Inventors: Richard Donald Maes, II, Robert Vernon Dusenberry, Eric S. Benson
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Patent number: 11671520Abstract: Compact timestamps and related methods, systems and devices are described. An encoder is configured to generate compact timestamps of the disclosure by sampling states of linear feedback shift registers (LFSRs). A decoder may be configured to determine timing information responsive to the compact timestamps.Type: GrantFiled: August 2, 2021Date of Patent: June 6, 2023Assignee: Microchip Technology IncorporatedInventor: Jason M. Sachs
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Patent number: 11669340Abstract: Example aspects include techniques for syncing configuration settings between incompatible operating systems. These techniques may include determining, via a first application, system-wide configuration information associated with a host system configuration parameter and a first configuration value of the host operating system, and transmitting a synchronization notification to a second application executing on a guest operating system, wherein the synchronization notification corresponding to the system-wide configuration information. In addition, the techniques may include configuring a guest system configuration parameter to a second configuration value based on the synchronization notification, and executing a third application on the guest operating system based on the second configuration value.Type: GrantFiled: February 23, 2021Date of Patent: June 6, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Kevin M. Kieselbach, Jeffrey Genovy
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Patent number: 11669477Abstract: A method for supporting TCM communication by a BIOS of an ARM server, including: setting an access mode of a LPC bus device to a 4-byte mode by means of a BIOS of an ARM server; causing the BIOS to perform data communication with a TCM chip of the LPC bus device in the 4-byte mode; in response to the BIOS reading a register by means of the LPC bus device, determining a type of the register; in response to determining that the type of the register is a specific FIFO register, changing a control register from the 4-byte mode to a single-byte mode, and performing single-byte read-write on the specific FIFO register; and in response to completion of read-write of the specific FIFO register, changing the control register to the 4-byte mode by means of the BIOS, and performing a read-write operation on other FIFO registers.Type: GrantFiled: September 28, 2020Date of Patent: June 6, 2023Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventor: Xiuqiang Sun
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Patent number: 11657011Abstract: Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.Type: GrantFiled: December 9, 2020Date of Patent: May 23, 2023Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Lei Guo, Jingdong Zhang, Jiangwei Wang
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Patent number: 11636051Abstract: A bus arbitration circuit includes a first bus port, a second bus port, a first output circuit connected to the first bus port, a second output circuit connected to the second bus port, a control circuit, and a switch circuit. The control circuit includes a first input port, a second input port, a control signal output port, and an output port. The first input port receives data of the first bus port, the second input port receives data of the second bus port, and data is outputted from the output port to an input port of the first output circuit. The switch circuit has an input port connected to the first bus port, a control port connected to the control signal output port of the control circuit, and an output port from which data of a host bus is outputted to an input port of the second output circuit.Type: GrantFiled: November 11, 2021Date of Patent: April 25, 2023Assignee: ABLIC Inc.Inventor: Biao Shen
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Patent number: 11625335Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.Type: GrantFiled: February 8, 2021Date of Patent: April 11, 2023Assignee: Cisco Technology, Inc.Inventors: Sagar Borikar, Ravikiran Kaidala Lakshman