Abstract: A system and method of converting an analog input signal to a linearized digital representation of the analog input signal. A measure of the analog input signal is compared to a threshold associated with a maximum dynamic range of a quantizer. A maximum amplitude of a random, analog dither signal is dynamically varied for perturbing quantization of the analog input signal in response to the comparison. The dynamically varied dither signal and the analog input signal are combined to obtain a dithered input signal. The quantizer converts the dithered input signal into the linearized digital representation of the analog input signal.

Abstract: A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.

Abstract: An interleaving successive approximation analog-to-digital converter (SAR ADC) with noise shaping having a first SAR block, a second SAR block, and a noise-shaping circuit is provided. The first and second SAR blocks take turns to sample an input voltage for successive approximation of the input voltage and observation of a digital representation of the input voltage. The noise-shaping circuit receives a first residue voltage from the first SAR block and receives a second residue voltage from the second SAR block alternately, and outputs a noise-shaping signal to be fed into the first SAR block and the second SAR block.

Abstract: A complex antenna configured to transmit or receive radio-frequency signals includes a first antenna unit and a second antenna unit. The first antenna unit is fixed to the second antenna unit with a first included angle, and the complex antenna does not have a closed annular structure.

Abstract: An analog-to-digital converter includes a first circuit and a second circuit. The first circuit includes a first quantizer that digitizes an input first analog voltage, has a function of subtracting an analog voltage generated based on the digitalized first value from the first analog voltage, has a function of amplifying a first analog residual voltage which is a result of the subtraction, and a first output drive amplifier that outputs the amplified first analog residual voltage. The second circuit includes a second quantizer that digitizes an input second analog voltage, has a function of subtracting an analog voltage generated based on the digitalized second value from the second analog voltage, has a function of amplifying a second analog-residual voltage which is a result of the subtraction, and a second output drive amplifier that outputs the amplified second analog residual voltage.

Abstract: A delta sigma modulator circuit comprises a forward circuit path including a first integrator stage and an analog-to-digital converter (ADC) circuit, wherein a transfer function of the forward circuit path includes a signal gain element of m, wherein m is a positive integer; an input path to the first integrator stage, wherein a transfer function of the input path includes a signal gain element of l/m; and a feedback circuit path operatively coupled to an output of the ADC circuit and an inverting input of an op amp of the first integrator stage, wherein the feedback circuit path includes at least a first digital-to-analog converter (DAC) circuit and a transfer function of the feedback circuit path includes a signal gain element of l/m.

Abstract: Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

Abstract: Disclosed herein is a method including receiving a stream of packets into a buffer, each packet having a processed video data portion and a page count portion, the processed video data portion being a result of a modulo operation performed on a word of video data, and the page count portion being a data page number on which the word of video data is to be placed. Each packet is read from the buffer, and an output packet including the video data portion and a data tag portion is generated therefrom. The data tag portion is associated with, but does not directly represent, the data page number where the word of video data of the processed video data portion or of video data of a processed video data portion of a next packet, is to be placed. Each data tag portion contains fewer bits than each corresponding page count portion.

Abstract: A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.

Abstract: An analog-to-digital converter of non-binary capacitor array with redundancy bits and its chip. The non-binary capacitor array with redundancy bits comprises a common-mode voltage, analog signal input, no less than one redundancy bit capacitor and multiple capacitors; each capacitor of capacitors with redundancy bits and multiple capacitors is connected in parallel between common-mode voltage and analog signal input and marked in a sequence from highest to lowest/lowest to highest bit; the sum of the capacitance of capacitors from the lowest bit capacitor to an random capacitor must be no less than the capacitance of the higher bit capacitor adjacent to the random capacitor. The ratio of the capacitance of each capacitor to the capacitance of unit capacitor is set to be positive. The capacitor array is applied into an analog-to-digital converter or fabricated as a chip.

Abstract: In an ultra-wideband (“UWB”) receiver, a received UWB signal is periodically digitized as a series of ternary samples. The samples are continuously correlated with a predetermined preamble sequence to develop a correlation value. When the value exceeds a predetermined threshold, indicating that the preamble sequence is being received, estimates of the channel impulse response (“CIR”) are developed. When a start-of-frame delimiter (“SFD”) is detected, the best CIR estimate is provided to a channel matched filter (“CMF”) substantially to filter channel-injected noise.

Abstract: Provided is an AD converter having a rail-to-rail input voltage range and being free of a missing code and monotonicity loss. A comparator includes a first comparator having an NMOS differential input stage, a second comparator having a PMOS differential input stage, and an output selection circuit configured to select any one of outputs of the two comparators. A correction circuit acquires in advance a first AD converted value in the case of using the first comparator and a second AD converted value in the case of using the second comparator with respect to the same input voltage to calculate a correction value, and performs correction processing based on the correction value to suppress an offset error between the first AD converted value and the second AD converted value.

Abstract: A modal antenna array is described where modal antenna elements capable of generating multiple radiation modes are used to form array radiation patterns. Nulls in the array radiation pattern can be formed and positioned by proper modal antenna element mode selection, with these nulls used to provide interference suppression or mitigation. The shift in array radiation pattern maxima generated by modal element mode selection can be used to improve communication system link quality by optimizing array radiation pattern characteristics. Specifically, a ring or circular array configuration is described where a simplified common feed port can be implemented to feed multiple modal antenna elements used to form the array. A switch can be used to connect or disconnect one modal element from the array, with this feature providing additional unique array beam states. The modal array can be commanded via a look-up table or algorithm.

Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

Abstract: A method of data compression includes obtaining binary sensor data having rows with multi-bit data samples. The rows are divided into data groups each including two or more samples. A precedent value is selected for the rows or respective precedent values are selected for each data group. A compressed row of compressed sensor data is generated from each row by calculating differences between the data sample and the precedent value for its associated data groups. A Compression Information Packet (CIP) is generated for each row including information for returning the binary sensor data that includes a compressed predicate indicating whether each data group is stored compressed, a data group size being a multi-bit value that stores a group size used for row compression, and a compressed word size that stores a dynamic range of the row compression. The compressed rows are stored as stored compressed data along with the CIPs.

Abstract: A wall-mountable wireless control device may include an antenna (e.g., a slot antenna or a hybrid slot-patch antenna) for transmitting and/or receiving radio-frequency signals, and may have a conductive material on a large amount (e.g., greater than or equal to approximately 85%) of a front surface of the control device. The wireless control device may operate consistently when installed with different types of faceplate assemblies (e.g., faceplate assemblies having metal and/or plastic components) and when installed with different types of electrical wallboxes (e.g., metal and plastic wallboxes). A faceplate comprising a conductive element may be installed on the wireless control device, such that the conductive element operates as a radiating element of the antenna. The wireless control device may comprise a conductive member (e.g., a conductive label or a conductive strap) extending around a rear enclosure of the wireless control device between opposite sides of a conductive yoke.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses for decompression using hardware and software. For example, in embodiment a hardware apparatus comprises an input buffer to store incoming data from a compressed stream, a selector to select at least one byte stored in the input buffer, a decoder to decode the selected at least one byte and determine if the decoded at least one byte is a literal or a symbol, an overlap condition, a size of a record from the decoded stream, a length value of the data to be retrieved from the decoded stream, and an offset value for the decoded data, and a token format converter to convert the decoded data and data from source and destination offset base registers into a fixed-length token.

Abstract: A duty cycle adjustment circuit includes: a delay circuit to delay an input clock signal to produce a delayed clock signal having a rising edge partially overlapping the rising edge of the input clock signal, the input clock signal oscillating between first and second values about a midpoint value; a blender circuit to blend the input clock signal and the delayed clock signal to produce a blended clock signal; a buffer circuit to buffer the input clock signal for an amount of time comparable to the blender circuit, to produce a buffered clock signal; and a combiner circuit to combine the buffered and the blended clock signals to produce an output clock signal that transitions to or remains at the first value when both the buffered and blended clock signals are on the first value side of the midpoint value, and otherwise transitions to or remains at the second value.

Abstract: A circuit (100) comprises an input terminal (141) which is configured to receive an analog input signal (142). The circuit (100) also comprises a combination element (601) which is configured to combine a number of time-displaced signal values of the input signal (142) to form an analog combination signal (144). The circuit (100) also comprises a quantizer (131) having a converter core which is configured to receive the combination signal (144) via passive charge redistribution from the combination element (601) and to convert it into a digital output signal (145). Such techniques can thus provide for an analog/digital conversion with filtering in the analog domain.

Abstract: Techniques for generating signals with arbitrary noise shaping are discussed. One example apparatus configured to be employed within a transmitter can comprise a noise shaper configured to: receive an input signal xq; and apply noise shaping to the input signal xq to generate a noise shaped output signal yq, wherein an in-band noise of the noise shaped output signal yq is below an in-band noise threshold of a spectral mask associated with the noise shaper, wherein an out-of-band noise of the noise shaped output signal yq is below an out-of-band noise threshold of the spectral mask, and wherein a noise of the output signal yq in each of a plurality of bandpass regions is below an associated noise threshold for that bandpass region of the spectral mask.