Abstract: A sigma delta analog to digital converter for converting an analog input into a digital output comprises a reference path for receiving a reference voltage. The reference path comprises a digital to analog converter. The digital to analog converter comprises a reference voltage input for receiving the reference voltage, wherein the reference voltage input comprises two contacts and wherein each contact is a beginning of a voltage line of two voltage lines. The digital to analog converter comprises a plurality of switches and a plurality of capacitors. The switches of the plurality of switches are configured to connect the digital to analog converter in a sampling phase with the reference voltage and to disconnect the digital to analog converter in an integrating phase from the reference voltage.

Abstract: Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.

Abstract: Systems and methods for sampling data in bandwidth constrained data acquisition systems are provided. More specifically, the method may include selecting an anti-aliasing filter corner frequency equal to a first frequency, selecting an oversampling rate that is greater than a data sample transmission bandwidth, wherein the data sample transmission bandwidth is a data sample transmission rate from a data acquisition system to a receiving entity for data samples acquired from a sensor and having a selected sample resolution, acquiring data samples at the oversampling rate with the data acquisition system, and transmitting a fraction of the acquired data samples in accordance with the data sample transmission bandwidth.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

Abstract: Systems, methods, and circuitries for converting an analog voltage to a digital signal are provided. In one example a method to convert an analog voltage into a binary sequence that represents the voltage includes two modes. In the first mode, in each cycle, values for a next two or more of consecutive most significant bits (MSBs) in the sequence are determined using M comparators, wherein M is equal to or greater than 3. In a second mode, in each cycle, M redundant comparison results are determined using the M comparators. A value for the LSB is determined based on the M redundant values. At an end of conversion, the sequence of N bit values is generated based on the MSBs and the LSB.

Abstract: An analog-to-digital conversion method may include: generating an initial comparison signal by storing adjacent pixel signals and comparing the adjacent pixel signals, and generating a first control signal based on the generated initial comparison signal; generating a reference comparison signal by comparing the adjacent pixel signals based on the reference signal and a ramp-up signal switched according to the generated first control signal, and determining a ramping direction according to the generated reference comparison signal and generating a second control signal; and performing data conversion by selecting any one of the ramp-up signal and a ramp-down signal according to the generated second control signal, and by comparing the selected ramp signal with a ‘difference value between the adjacent pixel signals’.

Abstract: A digital-to-analog converter (DAC) includes a plurality of resistive elements connected together in series to form a ring of resistive elements. A node is formed by each of the connections of adjacent resistive elements of the ring. Groups of parallel-connected switches are coupled to each node. A first switch of the group of switches is for selectively coupling a first power supply voltage terminal to the node. A second switch of the group of switches is for selectively coupling a second power supply voltage to the node. A third switch of the group of switches is for selectively coupling an output terminal to the node. A differential or single-ended analog output may be provided. Mismatch induced error is removed using a mismatch error shaping technique that shapes the errors outside a pass-band.

Abstract: A digital-to-analog converter (DAC) includes a plurality of segments, wherein the plurality of segments includes a first segment electronically coupled to each of the plurality of segments, wherein the first segment includes a predetermined number of most significant bits (MSB), a second segment electronically coupled to each of the plurality of segments, wherein the second segment includes a first predetermined number of least significant bits (LSB), and a third segment electronically coupled with each of the plurality of segments, wherein the third segment includes a second predetermined number of LSBs. Additionally, the DAC includes an all logic implementation.

Abstract: A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

Abstract: A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.

Abstract: A processor includes a memory hierarchy, buffer, and a decompressor. The decompressor includes circuitry to read elements to be decompressed according to a compression scheme, parse the elements to identify literals and matches, and, with the literals and matches, generate an intermediate token stream formatted for software-based copying of the literals and matches to produce decompressed data. The intermediate token stream is to include a format for multiple tokens that are to be written in parallel with each other, and another format for tokens that include a data dependency upon themselves.

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

Abstract: An analog-to-digital converter (ADC) using an amplifier-based noise shaping circuit. The amplifier-based noise shaping circuit generates a noise shaping signal. A comparator of the ADC has a first input terminal coupled to an output terminal of a capacitive data acquisition converter that captures an analog input, a second input terminal receiving the noise shaping signal, and an output terminal for observation of the digital representation of the analog input. The amplifier-based noise shaping circuit uses an amplifier to amplify a residual voltage obtained from the capacitive data acquisition converter and provides a switched capacitor network between the amplifier and the comparator for sampling the amplified residual voltage and generating the noise shaping signal.

Abstract: An analog-to-digital conversion (ADC) block includes: an amplifier block configured to receive two analog input signals and a primary-precision configuration signal and generate a first pair of differential signals by amplifying the two analog input signals according to a primary-precision gain that is programmably set by the primary-precision configuration signal; a configuration block configured to receive a fractional-precision configuration signal and generate a second pair of differential signals by amplifying the first pair of differential signals according to a fractional-precision gain that is programmably set by the fractional-precision configuration signal; and a differential analog-to-digital converter (ADC) including a voltage-controlled oscillator (VCO), two counters, and an error generator block. The VCO receives the second pair of differential signals and generates two pulse signals having frequencies that vary depending on a difference between the second pair of differential signals.

Abstract: In various embodiments, at least one analog-to-digital converter (ADC) channel circuit may be used to convert an analog input signal into an output digital signal. A comparator threshold adjustment circuit may pseudorandomly modify at least one comparator threshold. A postprocessing circuit may identify, based on outputs of the ADC channel circuits, an ADC coefficient and may modify an output digital signal based on the ADC coefficient. As a result, the ADC channel circuits may more accurately convert the analog input signal into an output digital signal, as compared to a system that uses ADC channel circuits but does not include a postprocessing circuit. Further, a similar result may be obtained, as compared to a system that uses a higher gain amplifier, a higher speed amplifier, or both, but does not modify the one or more outputs.

Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

Abstract: A digital to analog converter convert digital data in binary format to thermometer bit vectors. A first set of the thermometer bit vectors corresponds to most significant bits of the digital data and a second set of the thermometer bit vectors corresponds to least significant bits of the digital data. Connections of first current sources corresponding to the first set of the thermometer bit vectors and second current sources corresponding to the second set of the thermometer bit vectors are dynamically and randomly alternated to a first output line and a second output line. Calibration current is applied to the second current sources so a total current of the second current sources and the calibration current is within a predetermined range of an average current of the first current sources.