Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

Abstract: A data compression apparatus of the invention includes a data acquisition unit to acquire n integers from encoding data, an integer division unit to divide each integer of the n integers into a second integer represented by low-order bits whose number of divided bits is b and a first integer represented by high-order bits obtained by excluding the low-order bits from each integer of the n integers and to output n first integers and n second integers, a first encoding unit to encode and output the n first integers as a first code represented by binary data having a number of bits that is a natural-number times the number of unit bits of L, and a second encoding unit to encode and output the n second integers as a second code.

Abstract: An interleaved DAC utilizes a set of positive sub-DACs and a set of negative sub-DACs for converting digital inputs in parallel without return to zero. For each digital input, a positive sub-DAC performs conversion and drives its analog output for a duration of N/fs; and a negative sub-DAC performs conversion and drives its analog output for a duration of (N?1)/fs; and by a delay of 1/fs. By combining the outputs from the two sets of sub-DACs, the output from the positive sub-DAC is effectively removed when it is no longer needed at the combined output. As a result, the combined analog signal has each data point valid only for a duration of T, thereby achieving the desired data conversion speed of fs.

Abstract: Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.

Abstract: According to one aspect, a semiconductor device (1) includes: an input circuit (11_1) configured to receive an analog signal, the analog signal and a digital signal being selectively input; an input circuit (11_4) configured to be driven by a power supply common to the input circuit (11_1) and receive a digital signal, the digital signal and an analog signal being selectively input; an AD converter (15) configured to perform AD conversion of the analog signal input to the input circuit (11_1); an edge detection circuit (12) configured to detect an edge of the digital signal input to the input circuit (11_4); and a control unit (13) configured to execute predetermined processing on a result of the AD conversion by the AD converter (15) based on a result of the detection by the edge detection circuit (12).

Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: A wall-mountable wireless control device may include an enclosure, a bezel, a metal yoke, a slot antenna, a radio-frequency communication circuit, and one or more conductive elements. The bezel and the enclosure may define a space. The slot antenna may be located within the space defined by the enclosure and the bezel. The slot antenna may be configured to communicate radio-frequency signals. The radio-frequency communication circuit may be configured to transmit or receive the radio-frequency signals via the slot antenna. The one or more conductive elements may be electrically coupled to the yoke, and may be configured to re-radiate the radio-frequency signals transmitted by the slot antenna. The one or more conductive elements may include a conductive backer in electrical connection with the metal yoke, where in some instances, the conductive backer is electrically connected to the metal yoke via a single electrical connection.

Abstract: A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

Abstract: An analog-to-digital converter includes a ramp signal generation unit suitable for decreasing a voltage range of a ramp signal in reverse proportion to a multiple of a gain and repeatedly generating the ramp signal by the multiple of the gain; a comparator suitable for repeatedly outputting a comparison signal by the multiple of the gain in response to the ramp signal; and a counter suitable for performing a counting operation in response to the comparison signal.

Abstract: A multiple output, multiple impedance string digital-to-analog converter (DAC) circuit can provide a first output having a first resolution in response to a first digital input signal and a second output having a second resolution in response to a second digital input signal. A main impedance string and a secondary impedance string can be coupled using switching networks to provide a first DAC output. By coupling additional switches to the main impedance string and by sharing the main impedance string, a second DAC output can be realized.

Abstract: The disclosure relates to technology for query compilation in a database management system. A first execution time of code for at least one database query without applying a code generation method is estimated and in response to receiving the at least one database query, and for one or more code generation methods, a compilation cost and a second execution time of the code as modified by the code generation methods is estimated. A cost savings for each of the one or more code generation methods is calculated, where the cost savings is calculated as the first execution time less the second execution time of the code generation method, less the compilation cost of the code generation method. One of the code generation methods or the no code generation method with the highest cost savings is then selected.

Abstract: Circuitry for correcting non-linearity of an analog-to-digital converter. A non-linearity correction system for an analog-to-digital converter (ADC) includes coefficient storage, coefficient transformation circuitry, and correction circuitry. The coefficient storage is encoded with a first set of coefficients for correcting non-linearity of the ADC at a first sampling rate. The coefficient transformation circuitry is coupled to the coefficient storage. The coefficient transformation circuitry is configured to generate a second set of coefficients for correcting non-linearity of the ADC at a different sampling rate. The correction circuitry is configured to apply the second set of coefficients to correct non-linearity in output of the ADC while the ADC is operating at the different sampling rate.

Abstract: Data is compressed based on non-identical similarity between a first data set and a second data set. A representation of the differences is used to represent one of the data sets. For example, a probabilistically unique value may be generated as a new block label. Probabilistic comparison of the new block label with a plurality of training labels associated with training blocks produces a plurality of training labels that are potentially similar to the new block label. The Hamming distance between each potentially similar training label and the new block label is determined to select the training label with the smallest calculated Hamming distance from the new block label. A bitmap of differences between the new block and the training block associated with the selected training label is compressed and stored as a compressed representation of the new block.

Abstract: A circuit includes a first amplifying stage, a noise extraction circuit and a noise cancellation circuit. The first amplifying stage is arranged for receiving an input signal to generate an amplified input signal. The noise extraction circuit is coupled to the first amplifying stage, and is arranged for receiving at least the amplified input signal to generate a noise signal associated with noise components of the amplified input signal. The noise cancellation circuit is coupled to the first amplifying stage and the noise extraction circuit, and is arranged for cancelling noise components of the amplified input signal by using the noise signal generated by the noise extraction circuit, to generate a noise-cancelled amplified input signal.

Abstract: The present disclosure provides an analog readout preprocessing circuit for a CMOS image sensor and a control method thereof. The analog readout preprocessing circuit comprises an extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion capacitor network 1 configured to achieve readout and analog-to-digital conversion of signals output from the CMOS image sensor; an operational amplifier configured to utilize “virtual short” of two input terminals of the operational amplifier and the charge conservation principle, to achieve a function of extended count-type integration cycle-successive approximation hybrid analog-to-digital conversion, where the extended count-type integration can effectively reduce a thermal noise and a flicker noise within the image sensor; a comparator configured to compare voltages at two terminals to achieve a function of quantization of signals; and a control signal generator configured to provide control signals.

Abstract: Systems and methods for providing an output signal based at least in part upon an input signal and a clock signal in a manner in which jitter is avoided or diminished, including for example a digital-to-analog converter (DAC), are disclosed herein. In one example embodiment, such a system includes an output signal generating component, a first component having a first switch and a variable characteristic, and a plurality of second components each having a respective additional switch and a respective fixed characteristic. A value of the variable characteristic is set at least in part based upon input and clock signals so that, when the variable characteristic influences at least indirectly the generating of the output signal by the output signal generating component, the output signal attains a first level that at least indirectly depends upon a phase of the clock signal relative to the input signal.

Abstract: A method and apparatus are provided for implementing preemptive customized Codeset Converter Selection (CCS) on Software as a Service (SaaS) in a computer system. A codeset converter is automatically selected for operational modes, customer requests and service tasks which prompt the launching of the SaaS application. The CC selection is based upon history logs, content, and learned behavior performed as the application is launched and referenced without the user having to restart the session. Launching a new session is not needed for the enablement of the CC function.

Abstract: An analog to digital converter includes an error integration circuit configured to receive an input charge from a detector and to integrate a difference between the input charge and one or more feedback charge pulses to create an error voltage. A quantizer is in operable communication with the error integration circuit and is responsive to the created error voltage. An accumulator having a mantissa component and a radix component is in operable communication with the quantizer. A charge feedback device in operable communication with the quantizer and the radix component of the accumulator. The charge feedback device is configured to generate the one or more feedback charge pulses proportional to the radix component of the accumulator and an output of the quantizer. Digital focal plane read out integrated circuits including the analog to digital converter are also disclosed.

Abstract: Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.