Abstract: Methods of generating a gradient waveform, gradient waveform generators and magnetic resonance imaging systems are provided. In one aspect, a first digital value is obtained by quantizing and coding spatial position information of a voxel of a subject according to the number of preset quantization bits, wherein the number of the quantization bits are more than the number of allowed input bits for a DAC; a second digital value is determined to be inputted into the DAC according to the first digital value and the number of the allowed input bits for the DAC; a quantization error is determined according to the first digital value and the second digital value; an error accumulating value is updated by accumulating the quantization error to the error accumulation value; the second digital value corrected according to the error accumulation value; and the corrected second digital value is inputted into the DAC.

Abstract: Technology is described herein for encoding and decoding numbers. In one aspect, floating point numbers are represented as binary strings. The binary strings may be encoded in a manner such that if one bit flips, the average and maximum distortion in the number that is represented by the binary string is relatively small. In one aspect, 2^n binary strings are ordered across an interval [a, b) in accordance with their Hamming weights. Numbers in the interval may be uniformly quantized into one of 2^n sub-intervals. For example, floating point numbers in the interval [a, b) may be uniformly quantized into 2^n sub-intervals. These 2^n sub-intervals may be mapped to the 2^n binary strings. Thus, the number may be assigned to one of the 2^n binary strings. Doing so may reduce the distortion in the number in the event that there is a bit flip in the assigned binary string.

Abstract: A method and apparatus for measuring an elapsed time from a starting signal to an ending signal in a time-to-digital converter. Primarily, the invention calculates an amount of complete cycles from the starting signal to a starting edge of a next clock cycle or the next Nth clock cycle (N is a natural number great than one) after the clock cycle corresponding to the ending signal. The amount is multiplied by a cycle time of the coarse clock to obtain a coarse time value. A time residue is calculated from the ending signal to the starting edge. Finally, the time residue is subtracted from the coarse time value to obtain a required time.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor includes a pixel array suitable for outputting a pixel signal corresponding to incident light; a row decoder suitable for selecting and controlling pixels in the pixel array by row lines; a tracking voltage generator suitable for generating a tracking voltage; a plurality of successive approximation register (SAR) analog-to-digital converters suitable for analog-to-digital converting a pixel signal by repeatedly performing N times (where N is a natural number representing desired resolution) a process of comparing the pixel signal generated by the pixel array with the tracking voltage generated by the tracking voltage generator and modulating the pixel signal; and a control unit suitable for controlling operations of the row decoder, the tracking voltage generator, and the plurality of SAR analog-to-digital converters.

Abstract: Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.

Abstract: A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

Abstract: A domestic appliance includes at least one antenna which is integrated in a handle of the domestic appliance or arranged on a non-conductive wall region. The handle may constitute a door handle, or the at least one antenna may also be integrated in an additional handle of the domestic appliance.

Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

Abstract: An analog-to-digital and digital-to-analog conversion system using pulse-density-modulation (PDM) digital signals which minimize noise and optimize dynamic range by dividing a signal into multiple parallel pathways by apportioning a least significant range portion of an incoming signal to a low-path circuit and a most-significant portion of the incoming signal to a high-path circuit. The high-path circuit and low-path circuit can be separately level-modified to optimize dynamic range. Embodiments of the system can include an analog-to-digital conversion, a digital-to-analog conversion, or a complete analog-to-digital and digital-to-analog conversion system.

Abstract: A high voltage AC measurement method and circuit is disclosed to measure with zero offset and mirrored distortion based on hybrid chopping and fully differential signal path. There is a scheme with hybrid chopping and dual mixed signal paths. It applies high frequency chopping to the voltage measurement signal before the low-voltage signal conditioning, then samples and converts it to digital with two simultaneous ADCs, and finally demodulate the chopped signal by software. This technique not only reduces DC errors and drift but also cancels the distortion asymmetry caused by ADC non-linearity. The resultant DC accuracy and resolution can be significantly smaller than 1 LSB.

Abstract: An incremental analog to digital converter for digitizing an analog voltage including an Mth order delta sigma modulator, an Mth order digital decimation filter, a controller, and a digital combiner. The controller operates the modulator to convert the analog voltage into multiple digital samples, and operates the digital decimation filter to convert the digital samples into a preliminary digital output value. The controller further operates the delta sigma modulator during a residue phase for M clock cycles in which the modulator provides a digital residue value. The digital combiner combines the preliminary digital output value with the digital residue value to provide an initial digital output value. For an Mth order system, only M additional cycles are needed to extract the residual value to increase the resolution of the digital output by an amount based on the resolution of a modulator quantizer.

Abstract: A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.

Abstract: Analog-to-digital converters (ADCs) can be used inside ADC architectures, such as delta-sigma ADCs. The error in such internal ADCs can degrade performance. To calibrate the errors in an internal ADC, comparator offsets of the internal ADC can be estimated by computing a mean of each comparator of the internal ADC. Relative differences in the computed means serves as estimates for comparator offsets. If signal paths in the internal ADC are shuffled, the estimation of comparator offsets can be performed in the background without interrupting normal operation. Shuffling of signal paths may introduce systematic measurement errors, which can be measured and reversed to improve the estimation of comparator offsets.

Abstract: An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

Abstract: Microwave antennas having optimized performance are provided. The microwave antennas include a primary reflector having effective foci arranged in a generally circular or elliptic range around a central axis thereof, and a matching component filling a hole at a bottom center portion thereof. The structural parameters of the microwave antenna are tuned by an aperture field analysis method to optimize the overall performance.

Abstract: An antenna device is provided and includes a circuit board, a first linear antenna, and a second linear antenna. The circuit board includes a grounding pattern and a feeding point insulated from the grounding pattern. The first linear antenna is connected to the grounding pattern and includes a first inductive element positioned between distal ends of the first linear antenna. The second linear antenna is connected to the feeding point and capacitively coupled to one of the distal ends of the first linear antenna. The second linear antenna includes a second inductive element positioned proximate a middle section of the second linear antenna.

Abstract: A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.

Abstract: A system and method where a comparator is operatively coupled to an output of a Digital-to-analog Converter (DAC). The DAC may comprise a single DAC core or a plurality of interleaved DAC cores. The comparator is configured to capture properties of DAC core output. A digital engine is operatively coupled to receive output of the comparator and configured to calculate a cross-correlation between comparator output and input to the DAC core(s). The digital engine may be configured to determine if the skew of each DAC core is positive or negative and to determine if a skew correction term for the DAC core(s) should be decreased or increased, based on the skew of each DAC core being positive or negative, respectively. In interleaved DAC core devices, clock frequency sampling edges of the comparator may alternate between clock edges of each of the interleaved DAC cores.

Abstract: An integrator includes a first switch, a first capacitor, a second switch, a second capacitor, an amplifier, a third switch, a forth switch, a third capacitor, and a control circuit. The control circuit repeats a first phase and a second phase. In the first phase, the control circuit renders the first switch and the third switch to turn on and the second switch and the fourth switch to turn off. In the second phase, the control circuit renders the second switch and the fourth switch to turn on and the first switch and the third switch to turn off.