Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from narrow to wide with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Abstract: A semiconductor device includes a substrate, an isolation structure, a conductive structure, and a first contact structure. The isolation structure is disposed in the substrate. The conductive structure is disposed on the isolation structure. The conductive structure extends upwards from the isolation structure, in which the first contact structure has a top portion on the conductive structure and a bottom portion in contact with the isolation structure.

Abstract: The disclosed technology generally relates to a process of forming transistors with high-k dielectric layers, such as selectively high-k dielectric layers. The high-k dielectric layers, which may be used as the gate dielectric, may be selectively grown from two-dimensional semiconductor materials. The process may be adapted for various transistor structures such as planar transistors, three-dimensional transistors, and gate-all-around transistors. Further, the process may also be used to create stacked transistors. In one aspect, a method for manufacturing a semiconductor device includes forming a seed structure over a base layer, forming a two-dimensional (2D) semiconductor layer disposed on the seed structure, and selectively growing a high-k dielectric layer over the 2D semiconductor layer.

Abstract: Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

Abstract: In a method of manufacturing a semiconductor device, a first conductive pattern is formed in a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive pattern and the first ILD layer, a via contact is formed in the second ILD layer to contact an upper surface of the first conductive pattern, a second conductive pattern is formed over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view, a part of the via contact is etched by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer, and a third ILD layer is formed over the second ILD layer.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses.

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

Abstract: The present disclosure relates to a semiconductor mark and a forming method thereof. The semiconductor mark comprises: a previous layer mark comprising first patterns and at least one second pattern, the second pattern being located between adjacent first patterns, the first pattern being different from the second pattern in material property. Since the first pattern and the second pattern in the previous layer mark in the semiconductor mark according to the present disclosure are different in material property, during measurement, the first pattern and the second pattern are different in reflectivity for measurement light. Thus, the contrast of images of the first pattern and the second pattern obtained during measurement is improved, the positions and boundaries of the first pattern and the second pattern are clearly determined, and the measurement of the previous layer mark is more accurate.

Abstract: An optoelectronic component includes an optical transducer made of III-V semiconductor material and an optical scanning microelectromechanical system comprising a mirror. The optical transducer and the optical scanning microelectromechanical system are produced on a common wafer comprising at least a first layer made of silicon or silicon nitride with a thickness of less than one micron and wherein at least the mirror and its holding springs are produced. In a first variant, the mobile parts of the optical scanning microelectromechanical system are produced in various layers of silicon. In a second variant, the mobile parts of the optical scanning microelectromechanical system are produced in the layer of III-V semiconductor material.

Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.

Abstract: A semiconductor structure includes a substrate and a dielectric material disposed over the substrate. A void is disposed within the dielectric material. A dielectric liner is disposed along inner sidewalls of the dielectric material proximate to the void. An inner surface of the dielectric liner defines an outer extent of the void, and the dielectric liner includes an inner liner layer and an outer liner layer.

Abstract: A method of transferring a micro light emitting diode (LED) to a pixel array panel includes transferring the micro LED by spraying using an inkjet method, wherein the micro LED comprises an active layer comprising a first portion emitting light in a first direction and a second portion emitting the light in a second direction different from the first direction.

Abstract: A device structure may include an interconnect-level dielectric material layer located over a substrate, a first metal interconnect structure embedded in the interconnect-level dielectric material layer and including a first metallic barrier liner and a first metallic fill material portion, and an overlying dielectric material layer. An opening in the overlying dielectric material layer may be formed entirely within an area of the first metallic barrier layer and outside the area of the first metallic fill material portion to reduce plasma damage. A second metal interconnect structure contacting a top surface of the first metallic barrier liner may be formed in the opening. An entirety of a top surface the first metallic fill material portion contacts a bottom surface of the overlying dielectric material layer.

Abstract: A three-dimensional (3D) memory device includes interleaved conductive layers and dielectric layers. Edges of the conductive layers and dielectric layers define a plurality of stairs. The 3D memory device may also include a plurality of landing structures each disposed on a respective conductive layer at a respective stair. Each of the landing structures comprises a first layer of a first material and a second layer of a second material. The first layer is over the second layer. The second material is different from the first material.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

Abstract: A semiconductor device may include a source on a first side of a gate. The semiconductor device may include a drain on a second side of the gate, where the second side of the gate is opposite to the first side of the gate. The semiconductor device may include a first contact over the source. The semiconductor device may include a second contact over the drain. The semiconductor device may include an air gap over the gate between at least the first contact and the second contact. The semiconductor device may include at least two dielectric materials in each of a region between the air gap and the first contact and a region between the air gap and the second contact.

Abstract: Provided in the present application a display panel, including a substrate, wherein the substrate includes a display area, an aperture area, located in the display area; and a partition area, surrounding the aperture area and provided with at least one partition ring disposed around the aperture area, wherein a partition groove is disposed on at least one side of the partition ring, wherein the partition groove comprises a third partition groove, a first partition groove, and a second partition groove that are disposed on a side along a first direction away from the substrate in sequence, and communicated with each other, and the first partition groove is used to separate an organic material layer on a side wall of the second partition groove from another organic material layer on a side of the third partition groove.