Abstract: Generally, examples described herein relate to methods and processing systems for performing multiple processes in a same processing chamber on a flowable gap-fill film deposited on a substrate. In an example, a semiconductor processing system includes a processing chamber and a system controller. The system controller includes a processor and memory. The memory stores instructions, that when executed by the processor cause the system controller to: control a first process within the processing chamber performed on a substrate having thereon a film deposited by a flowable process, and control a second process within the process chamber performed on the substrate having thereon the film. The first process includes stabilizing bonds in the film to form a stabilized film. The second process includes densifying the stabilized film.

Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.

Abstract: The present disclosure relates to a display panel. The display panel may include a substrate. The substrate may include a display area, a dummy area inside the display area, and a boundary area between the dummy area and the display area on the substrate. The display substrate may further include an isolation protrusion on the substrate at the boundary area. The isolation protrusion may be configured to isolate a functional layer in the display area from the functional layer in the dummy area, and at least a side surface of the isolation protrusion facing the dummy area may be covered by an isolation inorganic layer.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.

Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

Abstract: A light-collecting unit having an inverted pyramid shape is described. The light-collecting unit has one or more outer light-collecting panel facing inward. The light-collecting unit also includes a first plurality of inner, light-collecting panels facing outward and a second plurality of inner, light-collecting panels facing inward. A flower base is configured to support the first plurality of inner, light-collecting panels and the second plurality of inner, light-collecting panels. The first plurality of inner, light-collecting panels is disposed on an outer facing side of the flower base and the second plurality of inner, light-collecting panels is disposed on an inner facing side of the flower base. The light-collecting unit may also include a light emitting element, such as an LED or fiber optic cable end. The light emitting element may provide infrared light to the light-collecting unit. The light emitting element may provide the light using pulse-wave modulation.

Abstract: A sealing resin composition contains an epoxy resin (A), a curing agent (B) having at least one amino group in one molecule, and an inorganic filler (C), wherein the inorganic filler (C) contains a first inorganic filler (C1) having an average particle size from 0.1 ?m to 20 ?m and a second inorganic filler (C2) having an average particle size from 10 nm to 80 nm, and a value obtained by multiplying a specific surface area of the inorganic filler (C), by a proportion of a mass of the inorganic filler (C) in a solid mass of the sealing resin composition, is 4.0 m2/g or more.

Abstract: There is provided a technique that includes a precursor vessel in which a liquid precursor is stored; a first heater immersed in the liquid precursor stored in the precursor vessel and configured to heat the liquid precursor; a second heater configured to heat the precursor vessel; a first temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; a second temperature sensor immersed in the liquid precursor stored in the precursor vessel and configured to measure a temperature of the liquid precursor; and a controller configured to be capable of: controlling the first heater based on the temperature measured by the first temperature sensor; and controlling the second heater based on the temperature measured by the second temperature sensor.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a first gas feeder, a first gas processor and a second gas feeder. The first gas feeder is provided above a stage on which a substrate is to be placed and feeds a first gas to the substrate. The first gas processor supplies high frequency power to the stage and renders the first gas fed from the first gas feeder into plasma. The second gas feeder is provided above the stage and feeds a second gas more difficult to render into plasma than the first gas to an outer periphery of the first gas having been rendered into plasma.

Abstract: Systems and methods are described for depositing a TiN liner layer and a cobalt seed layer on a semiconductor wafer in a cobalt metallization process. In some embodiments the wafer is cooled after deposition of the TiN liner layer and/or the cobalt seed layer. In some embodiments the TiN liner layer and cobalt seed layer are deposited in process modules that are part of a semiconductor processing apparatus that also includes one or more modules for cooling the substrate. In some embodiments the cobalt seed layer may comprise a mixture of TiN and cobalt, a nanolaminate of TiN and cobalt layers or a graded TiN/Co layer.

Abstract: A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Abstract: A structured plasma cell includes a first electrode including a first plurality of micro-cavities and a first plasma disposed within one or more micro-cavities of the first plurality of micro-cavities. The structured plasma cell also includes a second electrode including a second plurality of micro-cavities and a second plasma disposed within one or more micro-cavities of the second plurality of micro-cavities. The structured plasma cell also includes an inter-electrode gap disposed between the first electrode and the second electrode.

Abstract: A memory cell includes: a first transistor, having a first diffusion region coupled to a bit line and a first gate electrode coupled to a first word line; a second transistor, having a second diffusion region coupled to the bit line and a second gate electrode coupled to a second word line; and a third transistor, having a third diffusion region coupled to a fourth diffusion region of the first transistor, a fifth diffusion region coupled to a sixth diffusion region of the second transistor, and a third gate electrode coupled to a third word line; wherein the first transistor is arranged to have a first threshold voltage, the second transistor is arranged to have a second threshold voltage, and the second threshold voltage is different from the first threshold voltage.

Abstract: There is provided a plasma vessel in which a process gas is plasma-excited; a substrate process chamber which is in communication with the plasma vessel; a gas supply system supplying the process gas; and a coil installed to wind around an outer periphery of the plasma vessel and supplied with high-frequency power, wherein the coil is installed such that: a distance from an inner periphery of the coil to an inner periphery of the plasma vessel at a predetermined position on the coil is different from a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at another position on the coil; and a distance from the inner periphery of the coil to the inner periphery of the plasma vessel at a position at which an amplitude of a standing wave of a voltage applied to the coil is maximized is maximized.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a first gate strip and a second gate strip. The substrate has at least one first fin in a first region, at least one second fin in a second region and an isolation layer covering lower portions of the first and second fins. The first fin includes a first material layer and a second material layer over the first material layer, and the interface between the first material layer and the second material layer is uneven. The first gate strip is disposed across the first fin. The second gate strip is disposed across the second fin.

Abstract: A process chamber includes one or more vertical walls at least partially defining a chamber portion of the process chamber, and multiple zones located about a periphery of the one or more vertical walls, wherein one or more of the multiple zones extends from a top to a bottom of the one or more vertical walls. The process chamber further includes a plurality of temperature control devices, each thermally coupled to the one or more vertical walls in one of the multiple zones, and a controller coupled to the plurality of temperature control devices and configured to set temperatures of one or more of the plurality of temperature control devices to obtain temperature uniformity within 2% across a substrate located in the chamber portion.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the at least one of the second transistors transistor channel includes non-silicon atoms, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.