Patents Examined by Brook Kebede
  • Patent number: 11031489
    Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu
  • Patent number: 11018294
    Abstract: A method for regulating a phase transformation of a hydrogen-containing transition metal oxide comprises steps of: providing a hydrogen-containing transition metal oxide having a structural formula of ABOxHy, wherein the hydrogen-containing transition metal oxide is in form of a first phase, A is one or more of alkaline earth metal elements and rare-earth metal elements, B is one or more of transition metal elements, x is a numeric value in a range of 1 to 3, and y is a numeric value in a range of 0 to 2.5; soaking the hydrogen-containing transition metal oxide with a first ionic liquid capable of providing hydrogen ions and oxygen ions; and applying a gating voltage to the hydrogen-containing transition metal oxide with the first ionic liquid as a gate to regulate the phase transformation of the hydrogen-containing transition metal oxide.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 25, 2021
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Pu Yu, Nian-Peng Lu, Jian Wu, Shu-Yun Zhou
  • Patent number: 11018144
    Abstract: An anti-fuse cell includes a control device and an anti-fuse element is introduced. The control device includes a source node, a drain node and a gate node, wherein the gate node is electrically coupled to a word line and the drain node is electrically coupled to a bit line. The anti-fuse element includes a first conductive layer, a second conductive layer and a dielectric layer, wherein the dielectric layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer of the anti-fuse element physically stacks upon and directly contacts a metal layer that is electrically connected to the source node of the control device, and first conductive layer is electrically coupled to a program line through a via. An anti-fuse cell having multiple anti-fuse elements and a chip having a plurality of anti-fuse cells are also introduced.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11018191
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer and second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented and include replacement gate, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • Patent number: 11011495
    Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 18, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind Bhagavat, David Hugh McIntyre, Rahul Agarwal
  • Patent number: 11004719
    Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; and performing a bonding of a fourth level above the third level, where the fourth level includes a second single crystal layer, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having a same doping type.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 11, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 11004788
    Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hwi-Chan Jun, Seul-Ki Hong, Hyun-Soo Kim, Sang-Hyun Lee
  • Patent number: 10998472
    Abstract: A light emitting device includes: a light emitting element having an emission face and lateral faces; a wavelength conversion member having a first face and a second face which opposes the first face, the wavelength conversion member being disposed on the emission face of the light emitting element so that the first face faces the emission face; a reflecting member disposed on lateral face sides of the light emitting element and covering at least a portion of outer lateral faces of the wavelength conversion member, and a cover member disposed on an upper face of the reflecting member while being adjacent to peripheral ends of the wavelength conversion member. The cover member contains at least one of a reflecting substance and a coloring substance. A body color of the wavelength conversion member and a body color of the cover member are the same color or similar colors.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 4, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Hirosuke Hayashi
  • Patent number: 10998200
    Abstract: The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Mei-Yee Shek, Srinivas D. Nemani, Ellie Y. Yieh
  • Patent number: 10991721
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing molybdenum portions located over a substrate, memory stack structures extending through the alternating stack, and including a memory film and a vertical semiconductor channel, and a backside blocking dielectric layer of a dielectric oxide material including aluminum atoms and at least one of lanthanum or zirconium atoms which directly contacts the molybdenum portions.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Raghuveer S. Makala, Masaaki Higashitani
  • Patent number: 10984988
    Abstract: Provided are a method of manufacturing a ring-shaped member and the ring-shaped member. A method of manufacturing a ring-shaped member to be placed in a process chamber of a substrate processing apparatus includes arranging one silicon member and another silicon member to cause one abutting surface of the one silicon member and another abutting surface of the other silicon member to abut on each other, heating the one abutting surface and the other abutting surface through optical heating to melt silicon on a surface of the one abutting surface and silicon on a surface of the other abutting surface such that silicon melt is caused to flow into a gap between the one abutting surface and the other abutting surface, and cooling the one abutting surface and the other abutting surface to crystallize the silicon melt forming a silicon adhesion part.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 20, 2021
    Assignee: THINKON NEW TECHNOLOGY JAPAN CORPORATION
    Inventors: Atsushi Ikari, Satoshi Fujii
  • Patent number: 10982324
    Abstract: Coated semiconductor wafers are produced by introducing a process gas through first gas inlet openings along a first flow direction into a reactor chamber and over a substrate wafer of semiconductor material lying on a susceptor in order to deposit a layer on the substrate wafer, whereby material derived from the process gas precipitates on a preheat ring arranged around the susceptor; extracting the coated substrate wafer from the reactor chamber; and subsequently removing material precipitate from the preheat ring by introducing an etching gas through the first gas inlet openings into the reactor chamber along the first flow direction over the preheat ring and also through second gas inlet openings between which the first gas inlet openings are arranged, along further flow directions which intersect with the first flow direction.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 20, 2021
    Assignee: Siltronic AG
    Inventor: Joerg Haberecht
  • Patent number: 10978348
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 13, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Patent number: 10971655
    Abstract: One embodiment provides a semiconductor device comprising: a substrate; a first semiconductor layer disposed on the substrate; a second semiconductor layer disposed on the first semiconductor layer; a third semiconductor layer disposed on the second semiconductor layer; and a reflective layer disposed on the third semiconductor layer, wherein the part between the first and second semiconductor layers, the part between the third and second semiconductor layers, and the second semiconductor layer comprise a depletion region, and the conductivity of the first semiconductor layer and the conductivity of the third semiconductor layer are different from each other, and the second semiconductor layer comprises an intrinsic semiconductor layer.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 6, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Hyung Jo Park
  • Patent number: 10971436
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Patent number: 10964625
    Abstract: A device for direct liquid cooling is disclosed. The device includes a packaged assembly disposed on a substrate. The device also includes a metal channel layer having a plurality of channels disposed on top of the packaged assembly, and a top seal disposed on the metal channel layer. The top seal has at least one inlet and at least one outlet for direct liquid cooling. The metal channel layer includes copper or silver. The packaged assembly can also include silicon channels. In addition, the method of producing the device is also disclosed.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Google LLC
    Inventors: Padam Jain, Yuan Li, Teckgyu Kang, Madhusudan Iyengar
  • Patent number: 10957606
    Abstract: Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: March 23, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yuxia Chen, Chao He
  • Patent number: 10957813
    Abstract: In an embodiment, a method for producing a plurality of optoelectronic semiconductor components is disclosed, wherein the method includes inserting a plurality of optoelectronic semiconductor chips with a suitable orientation into a linear feeding device, conveying the optoelectronic semiconductor chips to an injection device having an outlet opening, encapsulating the optoelectronic semiconductor chips with at least one cladding layer in the injection device and pressing the encapsulated optoelectronic semiconductor chips out of the outlet opening, wherein a compound of optoelectronic semiconductor chips is formed in which the optoelectronic semiconductor chips are connected to one another by the at least one cladding layer and separating the compound into a plurality of optoelectronic semiconductor components each component having an optoelectronic semiconductor chip which is at least partially encapsulated by the at least one cladding layer.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 23, 2021
    Assignee: OSRAM OLED GMBH
    Inventor: Siegfried Herrmann
  • Patent number: 10950432
    Abstract: Provided is a method of depositing a thin film on a pattern structure of a semiconductor substrate, the method including (a) supplying a source gas; (b) supplying a reactive gas; and (c) supplying plasma, wherein the steps (a), (b), and (c) are sequentially repeated on the semiconductor substrate within a reaction space until a desired thickness is obtained, and a frequency of the plasma is a high frequency of 60 MHz or greater.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: March 16, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Yong Gyu Han, Dae Youn Kim, Tae Hee Yoo, Wan Gyu Lim, Jin Geun Yu
  • Patent number: 10947109
    Abstract: A method for producing a semiconductor component is proposed. The method includes providing a housing. At least one semiconductor chip is arranged in a cavity of the housing. Furthermore, an electrical contact of the semiconductor chip is connected to an electrical contact of the housing via a bond wire. The method furthermore includes applying a protective material on the electrical contact of the semiconductor chip and also on a region of the bond wire which is adjacent to the electrical contact of the semiconductor chip, and/or on the electrical contact of the housing and also on a region of the bond wire which is adjacent to the electrical contact of the housing. Moreover, the method also includes filling at least one partial region of the cavity with a gel.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: March 16, 2021
    Inventors: Mathias Vaupel, Bernhard Knott, Horst Theuss