Abstract: A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a first metal layer over a semiconductor substrate, and forming a first layer over the first metal layer. The first layer and first metal layer are etched to expose a sidewall of the first layer and a sidewall of the first metal layer, wherein the etching disburses a portion of the first metal layer to create an accumulation of material on at least one of the sidewall of the first layer or the sidewall of the first metal layer. At least some of the accumulation is etched away using an etchant comprising fluorine.

Abstract: A process for preparing a support comprises the placing of a substrate on a susceptor in a chamber of a deposition system, the susceptor having an exposed surface not covered by the substrate; the flowing of a precursor containing carbon in the chamber at a deposition temperature so as to form at least one layer on an exposed face of the substrate, while at the same time depositing species of carbon and of silicon on the exposed surface of the susceptor. The process also comprises, directly after the removal of the substrate from the chamber, a first etch step consisting of the flowing of an etch gas in the chamber at a first etching temperature not higher than the deposition temperature so as to eliminate at least some of the species of carbon and silicon deposited on the susceptor.

Abstract: A semiconductor device includes an active fin disposed on a substrate, a gate structure, and a pair of gate spacers disposed on sidewalls of the gate structure, in which the gate structure and the gate spacers extend across a first portion of the active fin, and a bottom surface of the gate structure is higher than a bottom surface of the gate spacers.

Abstract: Methods for depositing a metal containing material formed on a certain material of a substrate using an atomic layer deposition process for semiconductor applications are provided. In one embodiment, a method of forming a metal containing material on a substrate comprises pulsing a first gas precursor comprising a metal containing precursor to a surface of a substrate, pulsing a second gas precursor comprising a silicon containing precursor to the surface of the substrate, forming a metal containing material selectively on a first material of the substrate, and thermal annealing the metal containing material formed on the substrate.

Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the following steps. An integrated circuit component is provided on a substrate. An insulating encapsulation is formed on the substrate to encapsulate sidewalls of the integrated circuit component. A redistribution circuit structure is formed along a build-up direction on the integrated circuit component and the insulating encapsulation. The formation of the redistribution circuit structure includes the following steps. A dielectric layer and a plurality of conductive vias embedded in the dielectric layer are formed, wherein a lateral dimension of each of the conductive vias decreases along the build-up direction. A plurality of conductive wirings is formed on the plurality of conductive vias and the dielectric layer. An integrated fan-out package of the same is also provided.

Abstract: Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.

Abstract: A quantum dot including a core including a first semiconductor nanocrystal including a Group III-V compound, and a shell disposed on the core and including a semiconductor nanocrystal including a Group II-VI compound, wherein the quantum dots do not include cadmium, the shell includes a first layer disposed directly on the core and including a second semiconductor nanocrystal including zinc and selenium, a second layer, the second layer being an outermost layer of the shell and including a third semiconductor nanocrystal including zinc and sulfur, and a third layer disposed between the first layer and the second layer and including a fourth semiconductor nanocrystal including zinc, selenium, and optionally sulfur, and a difference between a peak emission wavelength of a colloidal solution of the quantum dot and a peak emission wavelength of a film prepared from the colloidal solution is less than or equal to about 5 nanometers (nm).

Abstract: A display device includes a substrate; a first electrode and a second electrode disposed in an emission area and a sub-region and spaced apart from each other in a first direction; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements disposed on the first insulating layer in the emission area, and including ends disposed on the first and second electrodes, respectively; and a second insulating layer disposed on the first insulating layer. The second insulating layer includes a fixing pattern; a support pattern portion; and a connection portion electrically connecting the fixing pattern and the support pattern portion, and the fixing pattern includes a first region that contacts an outer surface of the light emitting elements and a second region that does not contact the outer surface of the light emitting elements.

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.

Abstract: A display substrate includes a plurality of sub-pixels. The display substrate further includes: a base substrate; a plurality of temperature sensors disposed on a first side of the base substrate; and a light-shielding layer disposed on a peripheral side, a side proximate to the base substrate, and a side away from the base substrate, of a temperature sensor in the temperature sensors. The temperature sensor is configured to detect a temperature of at least one of the plurality of sub-pixels. The light-shielding layer is configured to shield light emitted to the temperature sensor.

Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.

Abstract: There is provided a technique that includes: removing a deposit that adheres to an interior of a process chamber by performing a cycle a predetermined number of times, the cycle including performing sequentially: (a) supplying a cleaning gas to the interior of the process chamber until an internal pressure of the process chamber rises to a first pressure range; (b) exhausting the interior of the process chamber and supplying the cleaning gas to the interior of the process chamber in parallel to maintain the internal pressure of the process chamber within the first pressure range; and (c) exhausting the interior of the process chamber until the internal pressure of the process chamber reaches a second pressure that is below the first pressure range.

Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.

Abstract: A method is provided for producing an electrically-powered device and/or component that is embeddable in a solid structural component, and a system, a produced device and/or a produced component is provided. The produced electrically powered device includes an attached autonomous electrical power source in a form of a unique, environmentally-friendly structure configured to transform thermal energy at any temperature above absolute zero to an electric potential without any external stimulus including physical movement or deformation energy. The autonomous electrical power source component provides a mechanism for generating renewable energy as primary power for the electrically-powered device and/or component once an integrated structure including the device and/or component is deployed in an environment that restricts future access to the electrical power source for servicing, recharge, replacement, replenishment or the like.

Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.

Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.

Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductive type, and a third silicon carbide region of a second conductive type, the first region being interposed between the second silicon carbide region and the third silicon carbide region. A first width of the first region in a second direction perpendicular to the first direction is 0.5 ?m or more than and 1.2 ?m or less. A second width of the second region in the second direction 0.5 ?m or more than and 1.5 ?m or less.

Abstract: A substrate processing method includes: providing a substrate including a first region and a second region into a chamber; forming a deposit film on the first region and the second region of the substrate by generating a first plasma from a first processing gas, and selectively etching the first region with respect to the second region by generating a second plasma from the second processing gas containing an inert gas. The first processing gas is a mixed gas including a first gas containing carbon atoms and fluorine atoms and a second gas containing silicon atoms.