Abstract: A method for producing a 3D semiconductor device, the method comprising: providing a first level, said first level comprising a first single crystal layer; forming first alignment marks and control circuits in and/or on said first level, wherein said control circuits comprise first single crystal transistors, and wherein said control circuits comprise at least two interconnection metal layers; forming at least one second level disposed on top of said control circuits; performing a first etch step into said second level; and performing additional processing steps to form a plurality of first memory cells within said second level, wherein each of said memory cells comprise at least one second transistors, and wherein said additional processing steps comprise depositing a gate electrode for said second transistors.

Abstract: A nitride-based electronic device includes an oxide cladding layer, a nitride cladding layer, and a nitride active region layer arranged between the oxide cladding layer and the nitride cladding layer. First and second metal contacts are electrically coupled to the nitride active region layer. The nitride-based electronic device can be formed in a system in which a non-reactive chamber is arranged between an oxide reaction chamber and a nitride reaction chamber so that oxide and nitride layers can be grown without exposing the device to the environment between growth of the oxide and nitride layers.

Abstract: A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, and where the additional processing steps include depositing a gate electrode simultaneously for the second and third transistors.

Abstract: A semiconductor manufacturing apparatus is provided including a beam shaper arranged on a light path of a laser beam and including a plurality of mask modules. The plurality of mask modules defines a light blocking region and a light transmitting region. At least one mask module of the plurality of mask modules includes a blocking plate configured to block a portion of the laser beam, and a driver is configured to move the blocking plate.

Abstract: An electrically programmable fuse structure and a semiconductor device are disclosed. The electrically programmable fuse structure comprises a cathode, a fuse link and an anode, the fuse link connecting the cathode to the anode, the cathode connected to the fuse link at a junction, wherein the cathode comprises a plurality of conductive branches arranged to form a converging side and a diverging side, and the converging side of the cathode is connected to the junction so as to be connected to the fuse link.

Abstract: Provided is a substrate with multilayer reflective film used to manufacture a reflective mask having a multilayer reflective film having high reflectance with respect to exposure light and little film stress. The substrate with multilayer reflective film is provided with a multilayer reflective film for reflecting exposure light, the substrate with multilayer reflective film comprising a multilayer film obtained by building up an alternating stack of low refractive index layers and high refractive index layers on a substrate, and the multilayer reflective film contains krypton (Kr).

Abstract: In an embodiment, a system includes: a base; and a rod set comprising multiple rods connected to the base, wherein each rod of the rod set comprises multiple fingers disposed in a vertically-stacked relationship to each other and separated respectively from each other by respective slots, wherein each slot is configured to receive a bevel of a wafer, and wherein each of the multiple fingers comprises a rounded end at a furthest extension.

Abstract: A structured plasma cell includes a first electrode including a first plurality of micro-cavities and a first plasma disposed within one or more micro-cavities of the first plurality of micro-cavities. The structured plasma cell also includes a second electrode including a second plurality of micro-cavities and a second plasma disposed within one or more micro-cavities of the second plurality of micro-cavities. The structured plasma cell also includes an inter-electrode gap disposed between the first electrode and the second electrode.

Abstract: According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [?1100] direction.

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.

Abstract: Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl4), hydrogen (H2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees Celsius; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

Abstract: A high performance, lead free, Ag paste thermal interface material (TIM) for die attachment and substrate bonding in electronic packaging includes: (i) multiscale silver particles, (ii) metal-coated carbon nanotubes (CNTs), (iii) a polymer, and (iv) a liquid carrier. The multiscale silver particles and metal-coated carbon nanotubes, which function as hybrid filler components, are uniformly dispersed within the TIM composition. The sintered TIM exhibits high density, high mechanical strength, and high thermal conductivity. The components of the liquid carrier including the solvent, binder, surfactants, and thinner are completely evaporated or burned off during sintering. Sintering of the TIM can be conducted at a relatively low temperature, without or with very low (<0.1 MPa) pressure, in open air and without vacuum or inert gas protection. The TIM can be utilized in substrate bonding not only on conventional metal-plated surfaces but also bare Cu substrate surfaces.

Abstract: A soft physiotherapy instrument includes a flexible sheet and a controller. The flexible sheet includes a first flexible layer, a second flexible layer, a plurality of functional layers located between the first flexible layer and the second flexible layer, and a plurality of electrodes electrically connected with the plurality of functional layers. The functional layer includes a carbon nanotube layer including a plurality of carbon nanotubes uniformly distributed. The flexible sheet is electrically coupled with the controller via the plurality of electrodes. A method for using the soft physiotherapy instrument is further provided.

Abstract: A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

Abstract: A film deposition method is provided. In the method, chlorine gas is activated in a plasma generator, and an adsorption inhibitor group is formed by adsorbing the activated chlorine gas on a surface of a substrate in a processing chamber. A source gas containing chlorine and one of silicon and a metal is adsorbed on a region without the adsorption inhibitor group of the surface of the substrate, and a nitride film is deposited by supplying a nitriding gas to the surface of the substrate and causing the nitriding gas to react with the source gas. The substrate on which the nitride film is deposited is carried out of the processing chamber, and an inside of the plasma generator is purged with activated oxygen gas.

Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

Abstract: A method and apparatus for on-line measurement of the wafer thinning and grinding force, related to the field of ultra-precision machining of semiconductor wafer materials. The grinding force measuring apparatus comprises a semiconductor wafer, a worktable, a bearing table, a thin film pressure sensor, and a data processing and wireless transmission module. The grinding force measuring method includes sensor calibration based on the testing device and on-line measurement of grinding force. Using the grinding force measuring device and method provided by the invention, the grinding force in the semiconductor wafer grinding process can be monitored in real time, which is of great significance for semiconductor processing and reducing grinding damage.

Abstract: Provided are a composition for depositing a silicon-containing thin film containing a bis(aminosilyl)alkylamine compound and a method for manufacturing a silicon-containing thin film using the same, and more particularly, a composition for depositing a silicon-containing thin film, containing the bis(aminosilyl)alkylamine compound capable of being usefully used as a precursor of the silicon-containing thin film, and a method for manufacturing a silicon-containing thin film using the same.

Abstract: Transition metal dichalcogenides (TMDs) are deposited by atomic layer deposition as thin layers on a substrate. The TMDs may be grown on oxide substrates and may have a tunable TMD-oxide interface. The TMD may be etched using an atomic layer etching technique.

Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed.