Abstract: A thin film transistor device including: a substrate; a gate electrode; an electrode pair composed of a source electrode and a drain electrode; a channel layer; and a passivation layer. The channel layer is made of an oxide semiconductor. The passivation layer includes a first layer, a second layer, and a third layer layered one on top of another in this order with the first layer closest to the substrate. The first layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride, the second layer is made of an Al compound, and the third layer is made of one of silicon oxide, silicon nitride, and silicon oxynitride.

Abstract: A display apparatus includes a display area and a non-display area around the display area. A substrate includes a plurality of pixels. Each pixel includes a first area through which light is emitted and a second area through which external light is transmitted. The plurality of pixels is arranged in a matrix in the display area. The substrate includes a transmission area, through which external light is transmitted, in the non-display area. An encapsulation thin film seals the substrate.

Abstract: The embodiments of the present invention provide a flexible display panel and a display device comprising the flexible display panel. The flexible display panel comprises a plurality of effective display regions, each effective display region comprising a pixel array; and at least one power supply lead region, which comprises at least one power supply lead in electrical connection with a power supply line of the flexible display panel; and the effective display regions and the power supply lead region are arranged alternately. For display devices using the flexible display panel according to the embodiments of the present invention, especially those having a larger size or higher resolution, the luminance uniformity can be improved and enhanced, and the advantages of the flexible display device can be further strengthened.

Abstract: In various embodiments, an optoelectronic component is provided. The optoelectronic component may include an electrode, and an organic functional layer structure formed for emitting an electromagnetic radiation or converting an electromagnetic radiation into an electric current. The electrode has a surface which is reflective with respect to the electromagnetic radiation, and wherein the organic functional layer structure is formed on or over the reflective surface of the electrode and is electrically coupled thereto. The reflective surface has a structuring.

Abstract: A barrier film on an organic electronic device. The barrier film comprises an inorganic polymeric silicon composition having Si—O—Si bonds which exhibit an asymmetric stretching Si-0 vibration frequency (AS1) ranging between 1200 cm?1 and 1000 cm?1, Si—O—H vibration frequency ranging between 950 cm?1 and 810 cm?1 and an —O—H ranging between 3400 cm?1 and 3700 cm?1 in which the ratio of peak areas for Si—O—H and —O—H vibration frequencies compared to the peak area of the Si—O—Si vibration frequency is less than 0.15. The barrier film exhibits a water vapor transmission rate between 1×10?2 g/m?2 day and 1×10?8 g/m?2 day.

Abstract: A display device including a substrate including a wiring electrode; a conductive adhesive layer including an anisotropic conductive medium, and disposed to cover the wiring electrode; and a plurality of semiconductor light emitting devices adhered to the conductive adhesive layer and electrically connected to the wiring electrode through the anisotropic conductive medium. Further, the conductive adhesive layer includes a first layer disposed on the substrate; a second layer deposited on the first layer and including the anisotropic conductive medium; and a third layer deposited on the second layer, to which the semiconductor light emitting devices are adhered. Further, at least one of the second layer and the third layer includes a white pigment configured to reflect light emitted by the semiconductor light emitting device.

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Abstract: The present disclosure includes bonded wafer structures and methods of forming bonded wafer structures. One example of a forming a bonded wafer structure includes providing a first wafer (202, 302) and a second wafer (204, 304) to be bonded together via a bonding process that has a predetermined wafer gap (216, 316) associated therewith, and forming a mesa (215, 315, 415) on the first wafer (202, 302) prior to bonding the first wafer (202, 302) and the second wafer (204, 304) together, wherein a height (220, 320, 420) of the mesa (215, 315, 415) is determined based on a target element gap (217, 317) associated with the bonded wafer structure.

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.

Abstract: A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

Abstract: The present technique relates to a semiconductor device and an electronic appliance in which the reliability of the fine transistor can be maintained while the signal output characteristic is improved in a device formed by stacking semiconductor substrates.

Abstract: Provided is a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with each side surface of the first oxide semiconductor film and the second oxide semiconductor film; a first insulating film and a second insulating film over the source electrode and the drain electrode; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with an upper surface of the gate insulating film and facing an upper surface and the side surface of the second oxide semiconductor film.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A dielectric collar structure can be formed prior to formation of an epitaxial channel portion, and can be employed to protect the epitaxial channel portion during replacement of the sacrificial material layers with electrically conductive layers. Exposure of the epitaxial channel portion to an etchant during removal of the sacrificial material layers is avoided through use of the dielectric collar structure. Additionally or alternatively, facets on the top surface of the epitaxial channel portion can be reduced or eliminated by forming the epitaxial channel portion to a height that exceeds a target height, and by recessing a top portion of the epitaxial channel portion. The recess etch can remove protruding portions of the epitaxial channel portion at a greater removal rate than a non-protruding portion.

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A deterioration of a gate threshold voltage, which is caused by a stress and a thermal hysteresis when wire bonding for a surface of an electrode layer of a semiconductor device is performed, can be suppressed. The semiconductor device includes a metallic film provided at a surface of a semiconductor chip, and a wire bonded to an upper surface of the metallic film. The metallic film has a plurality of grains, particle diameters of the grains are substantially equal to or more than a thickness of the metallic film.

Abstract: Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The capacitor devices include 2D material electrodes. The capacitor devices offer very fine granularity with high stacking possibilities which may be used in super capacitors and capacitor arrays. The devices include interleaved laminations 2D material electrode layers, for example graphene, and dielectric layers, for example Hafnium Oxide. In an embodiment a capacitor device includes 10,000 layers of interleaved graphene separated by 9,999 layers of HfO. Odd layers of the graphene are electrically connected to a first terminal and even layers of graphene are electrically connected to a second terminal of the capacitor device.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a first electrode layer, a second electrode layer, a third electrode layer, a fourth electrode layer, a first gate electrode layer, a second gate electrode layer, a gate insulating film, a first interlayer insulating film, a second interlayer insulating film. The first electrode layer is separated from the substrate in a first direction. The second electrode layer is separated from the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and the second electrode layer. The third electrode layer includes a first edge face. A second edge face of the first gate electrode layer at the second gate electrode layer side is along the first edge face.

Abstract: Exemplary embodiments provide for fabricating a biaxially strained nanosheet.