Patents Examined by Bryce P. Bonzo
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Patent number: 12105583Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.Type: GrantFiled: July 20, 2022Date of Patent: October 1, 2024Assignee: NXP B.V.Inventors: Neha Srivastava, Hemant Nautiyal, Andres Barrilado Gonzalez
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Patent number: 12066885Abstract: An information handling system includes a processor and an embedded controller. The processor executes operations while the information handling system is in an active power state. The embedded controller communicates with the processor. While the information handling system is in the active power state, the embedded controller detects a trigger event. In response to the trigger event, the embedded controller provides a ping command to the processor. Based on a response to the ping command not being received, the embedded controller determines a processor freeze, stores forensic data associated with the processor freeze, and stores an indication to perform a processor freeze recovery during a next boot operation.Type: GrantFiled: June 16, 2022Date of Patent: August 20, 2024Assignee: Dell Products L.P.Inventors: Craig L. Chaiken, Balasingh P. Samuel, Siva Subramaniam Rajan
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Patent number: 12056010Abstract: An information handling system may include a processor and first non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a basic input/output system (BIOS) core comprising BIOS core firmware sufficient to execute features of a BIOS of the information handling system to a particular portion of BIOS execution and an extension agent configured to identify and enumerate a firmware volume of a second non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a BIOS extension comprising BIOS extension firmware for executing completion of BIOS execution from the particular portion of BIOS execution.Type: GrantFiled: February 22, 2022Date of Patent: August 6, 2024Assignee: Dell Products L.P.Inventors: Shekar Babu Suryanarayana, Karunakar Poosapalli, Gowtham Moorthy, Piyush Dhamdhere
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Patent number: 12056029Abstract: Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.Type: GrantFiled: December 8, 2020Date of Patent: August 6, 2024Assignee: Intel CorporationInventor: Debendra Das Sharma
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Patent number: 12050519Abstract: A device receives a notification indicating a failure of a first server device responsible for a primary message queue that includes messages at a time of the failure. A second server device is responsible for a standby message queue to which the messages are replicated, where a position in the standby message queue and a message time are assigned to each of the replicated messages. The device obtains a record time that identifies the message time of one of the messages that was last obtained from the primary message queue prior to the failure, compares an adjusted record time and the message time of one or more of the messages of the standby message queue to determine a starting position in the standby message queue, and processes messages obtained from the standby message queue beginning at one of the messages assigned to the position that matches the starting position.Type: GrantFiled: January 4, 2023Date of Patent: July 30, 2024Assignee: Verizon Patent and Licensing Inc.Inventors: Amit Gupta, Sarvesh Agrawal, Vijaya Kosuri, Pramod Kalyanasundaram, Lakshmi Chakarapani, Srinivas S. Halembar
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Patent number: 12019528Abstract: An apparatus includes a communications interface and a management server. The management server is configured to access servers through the interface, determine that additional resources are needed for execution by a system, and determine that one of the servers is in a standby mode. In the standby mode, the server is powered down and a baseboard management controller (BMC) therein is only powered through a connection from the apparatus or another server of the network. The management server is configured to determine that additional resources for execution by the system from the server are to be activated and cause a wake-up signal to be sent to the BMC, wherein the wake-up signal is configured to cause the BMC to wake and provision the operating environment of the server.Type: GrantFiled: August 24, 2021Date of Patent: June 25, 2024Assignee: SOFTIRON LIMITEDInventors: Robert Drury, Andrew McNeil, Harry Richardson, Stephen Hardwick, Phillip Edward Straw, Alan Ott
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Patent number: 11994951Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register. The memory system may reset one or more components of the memory system based on the first indication and the second indication.Type: GrantFiled: May 6, 2022Date of Patent: May 28, 2024Assignee: Micron Technology, Inc.Inventor: Stephen Hanna
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Patent number: 11966307Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.Type: GrantFiled: May 23, 2022Date of Patent: April 23, 2024Assignee: NetApp, Inc.Inventors: Murali Subramanian, Sohan Shetty, Akhil Kaushik
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Patent number: 11921605Abstract: Approaches for managing applications in a cluster are described. In an example, a first agent may be executing on a first programmable network adapter card installed within a first computing node within a cluster. The first agent may isolate an application executing on the first computing node. Thereafter, the application may be managed by the second computing node.Type: GrantFiled: January 28, 2022Date of Patent: March 5, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Bhakthavatsala Naidu Kurapati, Venkatesh Nagaraj, Manish Ramesh Kulkarni
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Patent number: 11921570Abstract: An apparatus comprises a processing device configured to obtain monitoring data for devices comprising a plurality of features, determining two or more rankings of the features using two or more filter-based feature selection algorithms, and selecting a subset of the features based at least in part on the two or more rankings. The processing device is also configured to generate a failure prediction for a given one of the devices using at least one classifier that takes as input the selected subset of features, and applying a conformal prediction framework to the generated failure prediction to obtain a confidence measure indicating a quality of the generated failure prediction and a credibility measure indicating a quality of the monitoring data. The processing device is further configured to initiate one or more remedial actions based at least in part on the generated failure prediction, the confidence measure, and the credibility measure.Type: GrantFiled: September 21, 2020Date of Patent: March 5, 2024Assignee: Dell Products L.P.Inventors: Jayanth Kumar Reddy Perneti, Vindhya Gangaraju
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Patent number: 11914489Abstract: A method for redundant control in a distributed automation system, preferably a real-time automation system, for operating a client device of the distributed automation system is discussed. The method includes using the client device to monitor for the occurrence of a fault in communication between the client device and a first computing infrastructure that is part of the distributed automation system and operates the client device. The method may also include using the client device, once the fault occurs, to instruct a second computing infrastructure of the distributed automation system to operate the client device.Type: GrantFiled: June 7, 2022Date of Patent: February 27, 2024Assignee: Gestalt Robotics GMBHInventors: Jens Lambrecht, Thomas Staufenbiel, Eugen Funk, The Duy Nguyen
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Patent number: 11899547Abstract: A computing apparatus includes a transaction-record memory and a comparator. The transaction-record memory is to receive and store one or more sequences of transaction records, each transaction record including a unique transaction ID and a transaction payload. The comparator is to compare the payloads of transaction records having the same transaction ID, and to initiate a responsive action in response to a discrepancy between the compared transaction payloads.Type: GrantFiled: November 30, 2021Date of Patent: February 13, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Sharon Ulman, Eyal Srebro, Shay Aisman
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Patent number: 11892918Abstract: A patching operation on an availability group cluster having a plurality of nodes is disclosed. The patching operation is performed in a plurality of iterations, each including determining a current state of each of the plurality of nodes, selecting a next node based on the current state, and patching the next node. A secondary replica node is selected as the next node before the a primary replica node. Each secondary replica node is patched in accordance with a first priority, upon patching each of the secondary replica node, a failover target node for patching the primary replica node is selected, the failover target node is selected based on a second priority, and according to the second priority, a healthy synchronous secondary replica node of the plurality of nodes is selected as the failover target node before an unhealthy synchronous secondary replica node of the plurality of nodes.Type: GrantFiled: March 15, 2022Date of Patent: February 6, 2024Assignee: Nutanix, Inc.Inventors: Rohan Mohan Rayaraddi, Tarun Mehta
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Patent number: 11886307Abstract: The location of resources for file services are located within the same site, thereby eliminating or reducing performance issues caused by cross-site accesses in a stretched cluster environment. A file server placement algorithm initially places file servers at a site based at least in part on host workload and affinity settings, and can perform failover to move the file servers to a different location (e.g., to a different host on the same site or to another site) in the event of a failure of the host where the file servers were initially placed. File servers may be co-located with clients at a location based on client latencies and site workload. Failover support is also provided in the event that the sites in the stretched cluster have different subnet addresses.Type: GrantFiled: September 6, 2021Date of Patent: January 30, 2024Assignee: VMware, Inc.Inventors: Yang Yang, Ye Zhang, Wenguang Wang, Haifeng Li
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Patent number: 11886309Abstract: Methods, systems, and computer-readable media for a cell-based storage system with failure isolation are disclosed. A first subset of storage nodes is selected from a set of storage nodes of a data store and assigned to a first partition of data. Replicas of the first partition are stored using the first subset. A second subset of storage nodes is selected from the set of storage nodes and assigned to a second partition of data. The second subset is selected based (at least in part) on the membership of the first subset, and the second subset comprises at least one node not present in the first. Replicas of the second partition are stored using the second subset. Access requests associated with the first partition are routed to the first subset of storage nodes. Access requests associated with the second partition are routed to the second subset of storage nodes.Type: GrantFiled: May 6, 2022Date of Patent: January 30, 2024Assignee: Amazon Technologies, Inc.Inventors: Stanislav Pavlovskii, Jacob Carr
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Patent number: 11874744Abstract: A mobile phone having a flash memory reset function, which solves a malfunction of the mobile phone due to an abnormal state of a flash memory, and a flash memory control apparatus thereof. The flash memory control apparatus includes an application processor configured to provide the hold signal and the chip select signal for resetting when it is determined, on the basis of error information due to a read error of an integrated circuit operating by reading flash data, that an abnormal case due to a read error for the flash data has occurred more than a predetermined number of times; and a flash memory configured to reset the flash data when the hold signal and the chip select signal for resetting are received.Type: GrantFiled: August 27, 2021Date of Patent: January 16, 2024Assignee: Silicon Works Co., Ltd.Inventor: Myung Kyu Jeon
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Patent number: 11853176Abstract: In an example embodiment, a solution is provided to build a generic service failover framework that can be packaged as a library and implemented by many different microservices, whether on-premises or in the cloud. Each application can implement/add/hook this service to obtain the benefits of handling failover gracefully, as well as coming with some customizable options to provide a complete failover framework.Type: GrantFiled: June 9, 2022Date of Patent: December 26, 2023Assignee: SAP SEInventors: Sateesh Babu Chilamakuri, Sathya G, Ramya Nandakumaran
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Patent number: 11809293Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.Type: GrantFiled: November 23, 2021Date of Patent: November 7, 2023Assignee: Silicon Motion, Inc.Inventor: Li-Sheng Kan
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Patent number: 11803435Abstract: The disclosure relates to an MCU failure detection device and method. According to the disclosure, a device for detecting a failure in a microcontroller unit (MCU) comprises a receiver receiving first watchdog output information for determining a failure from an electronic control device, a determination unit determining whether the electronic control device has a failure based on the first watchdog output information, and upon determining that the electronic control device has the failure, transmitting a first reset signal to the electronic control device.Type: GrantFiled: July 28, 2021Date of Patent: October 31, 2023Assignee: HL Klemove Corp.Inventors: Jong Gyu Park, Chaiwon Yoon
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Patent number: 11803445Abstract: Boot failure protection on smartNICs and other computing devices is described. During a power-on stage of a booting process for a computing device, a boot loading environment is directed to install an application programming interface (API) able to be invoked to control operation of a hardware-implemented watchdog. During an operating system loading stage of the booting process, the application programming interface is invoked to enable the hardware-implemented watchdog. During an operating system hand-off stage of the booting process, a last watchdog refresh of the hardware-implemented watchdog is performed, and execution of the boot loading environment is handed off to a kernel boot loader of an operating system. The application programming interface may not be accessible after the hand off to the kernel boot loader.Type: GrantFiled: January 18, 2022Date of Patent: October 31, 2023Assignee: VMWARE, INC.Inventors: Andrei Warkentin, Jared McNeill, Sunil Kotian, Alexander Fainkichen, Shruthi Hiriyuru