Patents Examined by Bryce P. Bonzo
  • Patent number: 11372734
    Abstract: Database recovery is based on workload priorities. A database workload is divided into a plurality of workload groups. A workload group of the plurality of workload groups is selected for recovery, in which the selecting is based on a priority of the workload group. One or more recovery actions are performed for the workload group selected for recovery.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: June 28, 2022
    Inventors: Hong Mei Zhang, Xiaobo Wang, Shuo Li, Sheng Yan Sun, Mei Cai Zeng, Yi Bu Li
  • Patent number: 11360867
    Abstract: Systems and methods for re-aligning data replication configuration of a cross-site storage solution after a failover are provided. According to one embodiment, after a failover, the new primary distributed storage system orchestrates flipping of the data replication configuration of a peered consistency group (CG) to reestablish zero RPO and zero RTO protections for the peered CG. The primary causes the secondary distributed storage system to perform an atomic database operation on its remote configuration database to (i) delete an existing source configuration that identifies the secondary as a source of data replication; and (ii) persist a new destination configuration identifying the secondary as a destination of data replication.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 14, 2022
    Assignee: NetApp, Inc.
    Inventors: Murali Subramanian, Sohan Shetty, Akhil Kaushik
  • Patent number: 11360864
    Abstract: A vehicle safety electronic control system includes a first microcontroller having a lockstep architecture with a lockstep core and a second microcontroller having at least two processing cores. The lockstep core of the first microcontroller is configured to monitor and control outputs of said at least two cores of the second microcontroller.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 14, 2022
    Inventor: Norbert Kollmer
  • Patent number: 11354182
    Abstract: According to some embodiments, a system comprises a computer system comprising a processing unit, an interrupt controller, an internal watchdog, and a computer system reset interface. The system further comprises a watchdog controller comprising a secondary watchdog timer. Expiry of the computer system internal watchdog triggers the interrupt controller to cause the processing unit to collect debug information and triggers the watchdog controller to start a secondary watchdog timer. Expiry of the secondary watchdog timer triggers the watchdog controller to reset the computer system.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 7, 2022
    Inventors: Gaurav Gupta, Sachin Naik, Stefan Martin Schaeckeler, Surajit Ghoshal, Titian Lau
  • Patent number: 11341010
    Abstract: Techniques for rebuilding a failed drive of a plurality of drives are provided. The techniques include: (a) determining a number of empty data stripes that have been allocated from the plurality of drives; (b) applying a set of decision criteria to the determined number to yield a decision, wherein applying the set of decision criteria yields a first decision at a first time and a differing second decision at a second time; (c) in response to the first decision at the first time, deallocating an empty data stripe that was allocated from the plurality of drives to yield a plurality of data extents on disparate drives of the plurality of drives and continuing to rebuild the failed drive onto at least one of the plurality of data extents; and (d) in response to the second decision at the second time, pausing rebuilding the failed drive until applying the set of decision criteria yields the first decision.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 24, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Geng Han, Hongpo Gao, Jian Gao, Shuyu Lee, Vamsi K. Vankamamidi
  • Patent number: 11327838
    Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 10, 2022
    Inventors: Jung-Hwan Park, Tae-Young Oh, Hyung-Joon Chi, Kyung-Soo Ha, Hyong-Ryol Hwang
  • Patent number: 11327859
    Abstract: Methods, systems, and computer-readable media for a cell-based storage system with failure isolation are disclosed. A first subset of storage nodes is selected from a set of storage nodes of a data store and assigned to a first partition of data. Replicas of the first partition are stored using the first subset. A second subset of storage nodes is selected from the set of storage nodes and assigned to a second partition of data. The second subset is selected based (at least in part) on the membership of the first subset, and the second subset comprises at least one node not present in the first. Replicas of the second partition are stored using the second subset. Access requests associated with the first partition are routed to the first subset of storage nodes. Access requests associated with the second partition are routed to the second subset of storage nodes.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 10, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Stanislav Pavlovskii, Jacob Carr
  • Patent number: 11321199
    Abstract: Systems and methods for a service based disaster recovery system are disclosed. Embodiments may include the ability to configure and deploy a DR environment, including providing the ability to configure a DR service in the DR environment for one or more deployed primary services in a primary environment. An environment management database holds DR configuration data including the status of the deployed services. An environment manager may interact with the environment management database to determine an associated action for the services. The services may perform activation (e.g., wake up) or enter a standby mode (e.g., sleep) depending on the determined action.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: May 3, 2022
    Inventors: Shlomi Wexler, Itay Maichel, Shachar Radoshinsky
  • Patent number: 11321200
    Abstract: A Cable Modem Termination System (CMTS) providing high speed data services to one or more remote physical devices (RPDs). The CMTS executes entirely upon a plurality of protection groups. Each of the plurality of protection groups consists of a plurality of pods. A dynamic adjustment may be made as to which pods in a particular protection group are active. The dynamic adjustment is made response to determining that a particular protection group is experiencing a failure. This determination may be made by a high availability agent executing within a pod, of the particular protection group, that is experiencing the failure. Software associated with supporting a particular service group of the CMTS may be upgraded without upgrading the software associated with supporting the remainder of the plurality of service groups serviced by the CMTS.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 3, 2022
    Assignee: Harmonic, Inc.
    Inventors: Andrey Ter-Zakhariants, Ihor Kopieichyk, Nagesh Nandiraju, Robert Gaydos
  • Patent number: 11314524
    Abstract: The present disclosure relates to a method, apparatus and computer program product for managing service containers. According to example implementations of the present disclosure, there is provided a method for managing a group of service containers. In the method, in response to receiving a backup demand on a group of to-be-generated service containers, a configuration file for generating the group of service containers is built on the basis of the backup demand, the configuration file comprising scripts for installing backup agencies that perform backup operations to the group of service containers. An image file for initializing the group of service containers is loaded to at least one node in a service container management system so as to create a group of basic running environments.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 26, 2022
    Inventors: Samuel Li, Terry Xu, Eddie Dai, Eason Jiang, Zhongyi Zhou
  • Patent number: 11307967
    Abstract: Techniques for test orchestration are disclosed. A system executes multiple test execution plans, using instances of a same test container image that encapsulates a test environment and instances of at least two different test support container images that are specified by different user-defined test configurations and each configured to perform, respectively, one or more test support operations. To execute each of the test execution plans, the system generates a respective instance of the test container image and one or more test support containers. A particular test execution plan includes generating a test support container that is specified in a corresponding user-defined test configuration and that is different from any test support container specified in another user-defined test configuration.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 19, 2022
    Assignee: Oracle International Corporation
    Inventors: Yingfei Zhang, Gavin Chen, Eileen He, Eric Cao
  • Patent number: 11294750
    Abstract: In an embodiment, a system includes a plurality of memory components and a processing device. The processing device includes a command-lifecycle logger component that is configured to perform command-lifecycle-logging operations, which include detecting a triggering event for logging command-lifecycle debugging data, and responsively logging command-lifecycle debugging data. Logging command-lifecycle debugging data includes generating the command-lifecycle debugging data and storing the generated command-lifecycle debugging data in data storage.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Fangfang Zhu, Ying Yu Tai, Jiangli Zhu, Wei Wang
  • Patent number: 11288124
    Abstract: Methods, apparatus, systems and articles of manufacture for mitigating a firmware failure are disclosed. An example apparatus includes at least one hardware processor and first memory including instructions to be executed by the at least one hardware processor. The example apparatus further includes mask memory including a feature mask associated with a first firmware version, the feature mask identifying features of the first firmware version to be disabled. A platform firmware controller is to apply the first firmware version to the first memory for execution by the at least one processor, initialize the at least one processor using the feature mask, and in response to a detection of a failure, determine a first de-feature mask based on a second de-feature mask previously used by the at least one processor and the feature update mask; and initialize the processor using the first de-feature mask.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: March 29, 2022
    Assignee: Intel corporation
    Inventors: Sean Dardis, Karunakara Kotary, Michael Kubacki, Ankit Sinha
  • Patent number: 11281524
    Abstract: Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 22, 2022
    Inventors: Daniel Josef Egger, Don Greenberg, Douglas Templeton McClure, III, Sarah Elizabeth Sheldon, Youngseok Kim
  • Patent number: 11269805
    Abstract: Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: William J. Butera, Simon C. Steely, Jr., Richard J. Dischler
  • Patent number: 11269744
    Abstract: Failover methods and systems for a networked storage environment are provided. A filtering data structure and a metadata data structure are generated before starting a replay of a log stored in a non-volatile memory of a second storage node, during a failover operation initiated in response to a failure at a first storage node. The second storage node operates as a partner node of the first storage node to mirror at the log one or more write requests received by the first storage node prior to the failure, and data associated with the one or more write requests. The filtering data structure identifies each log entry and the metadata structure stores a metadata attribute of each log entry. The filtering data structure and the metadata structure are used for providing access to a logical storage object during the log replay from the second storage node.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: March 8, 2022
    Assignee: NETAPP, INC.
    Inventors: Parag Sarfare, Ananthan Subramanian, Szu-Wen Kuo, Asif Imtiyaz Pathan, Santhosh Selvaraj, Nikhil Mattankot, Manan Patel, Travis Ryan Grusecki
  • Patent number: 11269799
    Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 8, 2022
    Assignee: Arm Limited
    Inventors: R Frank O'Bleness, Erez Amit
  • Patent number: 11269728
    Abstract: A lifecycle management method, system, and computer program product include coordinating hardware, platform and application-level health checks for framework-independent and application-specific monitoring, failure detection, and recovery, coordinating the hardware, the platform, and the application-level health check by state-specific aggregation of distributed atomic status events, and creating a recovery policy based on the state-specific aggregation of the distributed atomic status events.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 8, 2022
    Inventors: Jayaram Kallapalayam Radhakrishnan, Vinod Muthusamy, Vatche Isahagian, Scott Boag, Benjamin Herta, Atin Sood
  • Patent number: 11256580
    Abstract: A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: February 22, 2022
    Inventor: Vincent Egger
  • Patent number: 11256562
    Abstract: A smart exception handler system for safety-critical real-time systems is provided. The system is configured to: receive a plurality of parameters at a plurality of nodal points in a real-time execution path; analyze the received parameters using a trained exception handling model, wherein the trained exception handling model has been trained using machine learning techniques to learn the critical path of execution and/or critical range of parameters at critical nodes, wherein the critical range of parameters comprises a learned threshold at a node; compute, using the trained exception handling model, a probability of fault at the critical nodes; compare the probability of fault at a critical node against a learned threshold at the node; and take proactive action in real-time to avoid the occurrence of a fault when the probability of fault at the node is higher than the learned threshold at the node.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 22, 2022
    Inventors: Prasun Das, Sreenivasan Govindillam K