Abstract: A method for forming an epitaxial region on a semiconductor wafer substrate of III-V compound composition. After deposition of a dielectric mask, a seed layer that includes indium is evaporated over the wafer. A layer of III-V material is then deposited over the surface of the wafer by MBE growth. The seed layer acts to create uniformly distributed nucleation cites that are randomly spaced over the surface of the dielectric material and causes a reduction of the surface mobility of the atoms during the epitaxial growth process so that the residual polycrystalline material form atop the dielectric mark exhibits enhance surface morphology. As a result, the direct placement of interconnects on the polycrystalline material is achieve and the costly and time-consuming step of removing both the polycrystalline material and the dielectric mask of the prior art is avoided.

Abstract: Method for producing a non-volatile memory cell and obtained memory cell.

Abstract: The invention relates to a method of determining the position of a p-n junction or the depth of penetration of the diffused electrode in the case of semiconductor devices produced by planar technology. According to the invention, a test pattern which comprises N pairs of windows, the spacing of which increases from pair to pair, is included in exposure. During the diffusion operation, the tubs produced overlap in the pairs of windows lying relatively close together, touch in one pair of windows (n.sub.o) and are separate from each other in pairs of windows lying relatively far apart. With the aid of a resistance measurement, the pair of windows (n.sub.o) in which the two tubs are still just touching is established, from which the lateral depth of penetration Y.sub.j is obtained as half the spacing of this pair of windows. From the lateral depth of penetration, the vertical depth of penetration X.sub.j can be established by means of the relationship X.sub.j =C.multidot.Y.sub.j.

Abstract: According to this invention, there is provided a method of manufacturing a semiconductor device. An element region and an element isolation region are formed on a semiconductor substrate of a first conductivity type. A first oxide film prospectively serving as a gate insulating film is formed in the element region. Thermal oxidization is performed after annealing is performed in nitrogen or ammonia atmosphere to nitrify an entire surface of the first oxide film. A predetermined region of a nitrified first oxide film is removed, and a second oxide film prospectively serving as a gate insulating film is formed in the predetermined region using the nitrified first oxide film as a mask. A gate electrode constituted by a polysilicon film is formed on each of the nitrified first oxide film and the second oxide film.

Abstract: Method for cleaning, with plasma, the surface of a substrate before another treatment, consisting:in a first cleaning step, in negatively polarizing the substrate and in subjecting it to an argon plasma, andin a second cleaning step, in subjecting the pretreated substrate to a hydrogen plasma, in order to ensure an efficient cleaning of the surface of the substrate.Application to the prior cleaning of a silicon substrate intended to receive an epitaxy.

Abstract: A method for manufacturing a CMOS semiconductor device having twin wells is disclosed. The method of manufacturing the CMOS device comprises the following. A silicon substrate is provided. A thick oxide layer is deposited and a first photoresist layer is coated sequentially on the silicon substrate. Then an N-well mask pattern is formed by removing a portion of the first photoresist layer, thereby defining an alignment-key region and N-well region and forming a thin oxide layer on such regions. An N-type impurity implantion process is then performed through exposed portions of the thin oxide layer into the silicon substrate, and the first photoresist layer portions remaining on the thick oxide layer are removed, to thereby expose the entire surface of the thick oxide layer. A second photoresist layer is coated on the entire surface of the oxide layer.

Abstract: A diamond thermistor is described. Surface portions of temperature sensing diamond of the thermistor are doped with impurity ions by ion implantation except for a sensing area thereof. A pair of electrodes are formed on the impurity regions in order to make good ohmic contacts with the diamond. The damage caused by the ion implantation is remedied by subjecting the diamond film to laser annealing.

Abstract: A method for rapid plasma hydrogenation of semiconductor devices is provided in which the hydrogenation is conducted in two steps, the first step being conducted at a hydrogenation temperature that is higher than the out-diffusion temperature at which a substantial amount of hydrogen diffuses out of said semiconductor device; and in the second step, the semiconductor device is cooled to a temperature at which out-diffusion is substantially avoided while the hydrogenation plasma is maintained.

Abstract: A mixture of at least two types of charged particles of ions having the same value obtained by dividing the electric charge of an ion by the mass of the ion, i.e., a mixture of charged particles including hydrogen molecular ions H.sub.2.sup.+ and deuterium ions D.sup.+, is accelerated in a charged particle accelerator. Since the mass spectrograph unit in the accelerator cannot divide the hydrogen molecular ions H.sub.2.sup.+ and the deuterium ion D.sup.+, both ions are accelerated together. When the hydrogen molecular ion H.sub.2.sup.+ collides against a silicon substrate, it is divided into two hydrogen ions 2H.sup.+. Since the hydrogen ion H.sup.+ and the deuterium ion D.sup.+ have different ranges in silicon, two regions including a great number of crystal defects are formed in the silicon substrate in one ion irradiating step. As a result, at least three regions of different lifetimes of carriers are formed at different depths of the semiconductor substrate.

Abstract: A nonvolatile semiconductor memory comprising a silicon semiconductor substrate and formed thereon a gate insulating film, wherein an ion belonging to the same Group IV in the periodic table as the ion of said silicon semiconductor substrate belongs is shot into said gate insulating film by ion implantation in a dose of not less than 10.sup.16 cm.sup.-2 to form an ion-implanted region therein in such a way that a peak of impurity density of the ion is present at the gate insulating film side from the interface between said semiconductor substrate and said gate insulating film.Also disclosed are an MOS integrated circuit comprising the nonvolatile semiconductor memory, and a method of making the nonvolatile semiconductor memory.

Abstract: A process for fabricating a p-channel VDMOS transistor includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming body regions. The threshold voltage of the VDMOS devices is adjusted subsequent to both gate formation and the high temperature, long duration body diffusion by implanting a suitable p-type dopant into the VDMOS channel through the insulated gate, after formation thereof. Since the gate is formed prior to threshold adjust, high temperature processing and long duration diffusions requiring the presence of the gate may be completed prior to threshold adjust, without risk to the adjusted device threshold.

Abstract: A diode which includes a first region formed in a polycrystalline silicon layer formed on a substrate. The diode has a predetermined width W and is one of an intrinsic region and a region including impurities at a low concentration therein, a second region and a third region including P-type impurities and N-type impurities therein respectively and both being oppositely arranged from each other with the first region therebetween in the polycrystalline silicon layer. Electrodes are electrically connected to the second region and the third region respectively, and further the film characteristic of the polycrystalline silicon layer and the predetermined width W thereof are determined in such a manner as to fulfill the following equation:W.sub.D .ltoreq.W.ltoreq.LL represents a carrier diffusion length and W.sub.

Abstract: An array of finned memory cell capacitors on a semiconductor substrate includes: a) an array of electrically insulated word lines atop a semiconductor substrate; b) first and second active regions adjacent the word lines; c) capacitor storage nodes electrically connecting with the first active regions, individual capacitor storage nodes including: i) a layer of first conductive material conductively connecting with a first active region, the layer of first conductive material having opposed outer lateral edges, and ii) a layer of conductively doped storage node polysilicon overlying and conductively connecting with the layer of first conductive material, the storage node polysilicon projecting laterally outward beyond the outer lateral edges of the first conductive material to define opposing storage node capacitor fins projecting laterally above adjacent word lines; d) a layer of capacitor dielectric electrically connecting with the storage node capacitor fins; e) a layer of electrically conductive cell poly

Abstract: The present invention provides a method of forming fuse ribbons between conductive layers on a semiconductor device. The formation of these fuse ribbons may be at different levels of multiple level integrated circuits. The fuse ribbons are formed in a more precise manner than can be obtained conventionally. Resistance control can be easily achieved and significant decreases in dimensions and the use of less fuse material can be achieved.

Abstract: A method of producing a highly reliable mask ROM and the product produced by the method are disclosed. The method is characterized by comprising the steps of forming low doped source-drains to relax the electric field between the gate electrode and drain, thereby suppressing the creation of hot carriers, and of depositing dielectrics of a predetermined thickness between neighboring gates to control the projection range of impurities implanted into the source-drain region of the bit into which data is to be written, the thickness of the dielectrics being determined such that the projection range does not exceed the junction depth of the source-drain in order to preclude the formation of parasitically doped layers which cause punch-through across an unwritten transistor.

Abstract: A process for preparing a semiconductor device comprises exposing at least a part of the main surface of a semiconductor substrate, forming a layer comprising the same main component as the above substrate, forming a flattening agent layer on the surface of said layer, removing the above layer and the flattening agent layer at the same time and injecting an impurity after said removing step.

Abstract: A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.

Abstract: Two process flows are disclosed for the stacked etch fabrication of an EPROM array that utilizes cross-point cells with internal access transistors. In each process flow, the edges of the poly 1 floating gates parallel to the poly 2 word line are self-aligned to the word line, eliminating parasitic poly 2 transistors and process requirements for coping with such transistors.

Abstract: A thyristor (38) is formed over an insulating layer (44). A gate (70) is operable to create a depletion region through the semiconductor layer (46) in which the thyristor (38) is implemented in order to turn the thyristor off. Isolation regions (48, 52) prevent operation of the thyristor from affecting adjacent devices.

Abstract: A fabrication process includes at least a step of low pressure CVD for depositing an upper silicon oxide layer on a silicon nitride layer which is formed through a lower silicon oxide layer on a silicon substrate, a next step of forming a gate electrode on the second oxide layer, and a further step of selectively removing the second oxide layer and instead forming a similar silicon oxide layer anew. This process can meet the demand for device miniaturization, improve the C-V characteristic of a MOS capacitor and provide uniform insulating layers.