Abstract: Decoder and method utilizing logic circuitry for decoding multi-bit digital signals. An input decoder decodes subsets of the input signals to provide a plurality of intermediate signals which are selectively combined to provide output signals which represent a desired decoding of the input signals. The intermediate signals are applied to generally parallel bus lines which extend centrally of the substrate on which the decoder is constructed. The logic circuits are arranged in blocks along both sides of the bus lines, with all of the bus lines extending past all of the logic blocks, and conductors extending transversely of the bus lines carry the appropriate intermediate signals from the bus lines to the logic blocks.

Abstract: A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed.

Abstract: An ADPCM coder (100) converts a linear PCM input signal representative of PCM encoded speech or voiceband data into a quantized n-bit differential PCM output signal. Samples of the PCM input signal are delivered to a difference circuit (11) along with a signal estimate of the same derived from an adaptive predictor (12). The resultant difference signal is coupled to the input of a dynamic locking quantizer (DLQ). A quantized version of the difference signal is delivered from the output of said quantizer to an algebraic adder (17) where it is algebraically added with the signal estimate. The result of this addition is coupled to the input of the adaptive predictor, which in response thereto serves to generate the next signal estimate for comparison with next PCM sample. The adaptive quantizer has two speeds of adaptation, namely, a fast speed of adaptation when the input linear PCM signal represents speech and a very slow (almost constant) speed of adaptation for PCM encoded voiceband data or tone signals.

Abstract: An analog-digital converter designed to provide digital data by converting analog input voltage signals into pulse signals by a voltage-frequency converter, and counting said pulse signals by a counter, the improvement being that the A-D converter comprises a sequence controller which selectively supplies low level- or high level- input voltage signals to the A-D converter before analog input signals being measured are received therein.

Abstract: Numeral representing signals are converted between data coding formats employed externally and internally of a central processing unit of a data processing system. By a treatment internal to the central processing unit, a numeral representing signal supplied to the unit in one of several external data coding formats is converted into a numeral representing signal having single internal data coding formed. By a treatment internal to the central processing unit, a numeral representing signal derived by the unit in the single internal data coding format is converted into a signal in a selected one of the several external data coding formats.

Abstract: A binary-coded-decimal to binary converter employs a selection network to which the binary coded decimal digits are applied, the digits being selected in pairs of increasing order of decimal denominational significance to be passed to the address lines of a pair of memory elements, the locations of which contain the binary terms equivalent to the decimal digits from which the particular location address is derived. In order to increase the effective utilization of the memory elements, the binary code components specifying at least one of the decimal digits are manipulated by the selection network, for example by conversion to complementary form, before being applied to the address lines.

Abstract: Apparatus for decreasing effect of transition of more significant bits in D/A converter reference of A/D converter. A pair of D/A converters are connected in tandem to eliminate transition of more significant bits of half scale. Also, three D/A converters are connected in parallel with each being offset from one another so that the effect of bit transition is minimized and occurs at different steps in analog output.

Abstract: A step data to synchro converter for coupling one of a plurality of different step data transmitters to one of a plurality of different synchro receivers. The output of the step data transmitter is applied to an interface circuit and processed into a three bit binary code suitable for actuating a plurality of switching means. The switching means selectively apply an in-phase and an out-of-phase output of a transformer, which is responsive to the synchro receiver's reference voltage and frequency source, to a plurality of transformers associated with the input stator windings of the synchro receiver. The output of the plurality of transformers is a drive signal which satisfactorily approximates synchro data.

Abstract: A sequence of or controls pulse-transfer stages supplies or controls pulses between a start limit and a stop limit in the sequence. The device whose position is to be encoded selects and controls a responsive means in a limiting stage. Each stage has a pulse-control device responsive to the selector or in itself incorporates the selector-responsive pulse-control function, being arranged to serve in different embodiments as a start limit or as a stop limit. In one example, the start limit is the initial stage of the sequence and the selected stage is the stop limit. In an alternative, the selected stage is the start limit and a pulse-transfer stage at or near the end of the sequence is the stop limit. An encoding counter counts pulses between the start and stop limits. The pulse-control devices have a prescribed physical arrangement, which is a circle in the case of a shaft position encoder, so that the counter provides a code that represents the position of a shaft.

Abstract: An encoder system which provides non-power of two, unambiguous, even counts, the system having a modular configuration to permit a substantial portion of the system to comprise standardized modules, wherein modifications to a minimum of modules provide a wide range of different system counts, the system utilizing a truncated, symmetric, unit step code sequence and a division of processing functions among modules which permits the user to select among system outputs having a number of different processing levels.

Abstract: A device for introducing digital data into a medium having bivalent or multivalent states and having a coding device and a commutation device. The coding device receives under the control of a first clock pulse series, data signals and forms therefrom a number of code bits which are combined as an input to the commutation device. The coding efficiency is smaller than 1. Under the control of a second clock pulse series, the commutation device switches each input to apply the code bits to a number of channels of the medium, so that for each channel certain code restrictions are satisfied.

Abstract: A communication device, wherein a state of coupling of a signal to be emitted and signal to be received is controlled by mounting and dismounting of a coupler, then the signal to be emitted is introduced as an input from an input device of a terminal device, while the signal to be received is produced as an output to an output device of the terminal device, and further, at the time of mounting the coupler, communication is carried out with communication lines through the coupler, while, at the time of dismounting the coupler, the information input from the input device is recorded or displayed by the output device.

Abstract: An analog scan signal having a repetitive background waveform is converted into a multi-level signal through a peek hold circuit, a converter, a digital memory and a discriminator. The peak hold circuit detects and holds the peak voltage of the current scan lines. The background waveform is normalized by the peak voltage and converted into a digital signal in the converter and stored in the memory. The analog scan signal is discriminated in the discriminator on the basis of a reference voltage produced with the normalized background waveform read out of the memory and converted in the converter and with the current peak voltage supplied from the peak hold circuit.

Abstract: A method and apparatus is described for dynamically testing the overall performance characteristics of digital-to-analog converts and analog-to digital converters which involve excitation of the converters by an orthogonal function signal. Specifically the method comprises dynamically exercising a converter with an analog or digital signal pattern characterized by the sum of a set of mutually orthogonal functions, the sum having substantially uniform amplitude distribution among allowable states (maximum entropy), and simultaneously examining the output response of the converter for a plurality of basic performance parameters. The basic performance parameters typically include distortion, linearity and optimum gain. The simultaneous examination involves sorting out expected responses to simultaneously applied orthogonal signals. The method yields a relatively complete statistical description of the performance characteristics. The preferred excitation is based on the Walsh functions.

Abstract: A multiplexed analog-to-digital converter is provided for use in an inertial navigation system comprising a multiplexer, a buffer, a feedback stabilized ramp generator and a comparator controlling a gated counter whose digital output is representative of the analog input signal.

Abstract: The analog output from a local DAC comprising an LDAC and an MDAC, in which the full scale of the LDAC is always larger than the quantized level of the MDAC, is compared with an input analog signal which is sampled and held. A digital code obtained by successive approximation in accordance with the result of the comparison is stored in a successive approximation register. A shift code for calibrating the D/A conversion in the local DAC by shifting the digital code which is previously allotted to each digital code is stored in a shift code generating circuit (ROM). The digital code from the successive approximation register is digitally shifted in accordance with the shift code by a code shift circuit such as a digital adder/subtractor to obtain an A/D conversion output. An analog to digital converter with a high accuracy and an improved conversion speed is inexpensively fabricated in the form of a one chip LSI by a usual CMOS process.

Abstract: In a data compressing system, a sampling circuit samples an audio signal from a signal generator at a given period, and an A/D converter converts the sampled data into corresponding digital data. A differential circuit differentiates the digital sampled data to produce differential sampled data. The differential sampled data is segmented into sampling data trains each including the number of the sampled data corresponding to the audio signal for one second. The sampled data trains for 100 seconds are added by an adder in a manner that the sampled data in each of the sampled data trains are arranged in a random fashion. The data train formed by the addition is used, as compressed data, for communication or reproduction of signals.

Abstract: An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 1 zero and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that map 2 bits of unconstrained into 3 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of two future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 5 bits. The hardware implementation is extremely simple and can operate at very high data speeds.

Abstract: A digital to analog converter comprising a first digital to analog converter for generating an output signal of higher order bits; a second digital to analog converter for generating a full scale output as an output signal of lower order bits which is always larger than the output value (1 LSB) corresponding to one bit of a digital input at the least significant bit of the first digital to analog converter; adding means for adding the output signal from the first digital to analog converter to the output signal from the second digital to analog converter to form an analog output signal; and a code converter for applying to the first and second digital to analog converters an input code obtained by shifting a digital input signal applied to the first and second digital to analog converters by a given value such that the relationship between the digital input signal and the analog output signal is made substantially linear.

Abstract: In a method and apparatus for transmitting digital signals by means of signal generators by initially converting a double current pulse train, under control of bit clock pulses and before transmission, into a first unipolar pulse train composed of pulses corresponding to all positive transmission pulses and into a second unipolar pulse train composed of pulses corresponding to all negative transmission pulses, the pulse trains are code converted independently of the duration of the bit clock pulses for producing a converted signal having a first transmitting amplitude in correspondence with each pulse of the first pulse train and a second transmitting amplitude in correspondence with each pulse of the second pulse train, the second amplitude differing from the first, and the converted signal is applied to a signal generator for producing an output signal corresponding to the converted signal and in which the transmitting amplitudes corresponding to both unipolar pulse trains vary the output signal in the same