Abstract: A D.C. stabilized analog-to-digital converter of the type having a coarse converter responsive to a supplied analog signal for converting the analog signal to a coarse digital signal representation thereof, a reconverter for reconverting the coarse digital signal representation to a coarse analog signal and for determining the difference between the coarse analog signal and the supplied analog signal, and a fine converter responsive to the determined difference for converting said difference to a fine digital representation of the supplied analog signal. A reference signal is periodically supplied to the coarse converter such that this supplied reference signal is converted to a coarse digital signal representation thereof, the coarse digital signal representation of the reference signal is reconverted to a coarse analog reference signal and the difference between this coarse analog reference signal and the periodically supplied reference signal is determined.

Abstract: A bit cell is presented which can provide a small weighted current without loss of switching speed. The bit cell contains a switch which is responsive to an applied control signal to direct the weighted current to an output or to divert it away from the output. Supplementary currents are supplied to the switch to provide sufficient current to the switch to charge and discharge parasitic capacitances of the switch within the switching time of the control voltage. The supplementary currents maximize switching speed at a given power dissipation and produce a constant offset current at the switch output. A D/A converter is presented which utilizes a plurality of such bit cells to maximize the speed of D/A conversion. The offset currents are eliminated from the converter output so that the output current is proportional to the digital input.

Abstract: An integrating digital-to-analog converter circuit includes an operational-amplifier based integrator, a plurality of constant current sources each providing constant current at a respective different level, and a plurality of switches each associated with a respective current source for coupling the same to the integrator. A plurality of digital counters are arranged to hold a predetermined portion of an n-bit digital word loaded therein and to count clock pulses until their contents reach a predetermined count. At those times, a carry pulse is generated in each such digital counter and the associated switch is opened to cut off the associated current source. Such a digital-to-analog converter circuit can convert data words of relatively high bit length without the need for an excessively high frequency clocking signal.

Abstract: In a chart recorder using a fiber optics tube, a method and apparatus for recording signals on a record medium such as a photo sensitive paper by simultaneously scanning a beam in the fiber optics tube both horizontally and vertically.

Abstract: For converting a digital value into an analog value, the digital value is first converted into a binary number and then selected auxiliary pulse trains corresponding to the binary number are used to control a switch which connects a capacitor alternatively to a reference voltage source or to ground to charge the capacitor to a voltage which corresponds to the converted analog value. The pulses in the auxiliary pulse trains associated with each binary position are grouped into pulse groups and the pulse groups of each pulse train are distributed over the duration of a conversion period in such a manner that during the superimposition of auxiliary pulse trains the number of pulse groups is not increased but the existing pulse groups are widened by being placed next to each other. In addition, the width of the single pulses forming the pulse groups is doubled so that the pulse groups are transformed into width-modulated pulses.

Abstract: For the dynamic compensation of the offset voltage in such converters each non-inverting comparator input (+) is connected via a first transfer transistor (T11, T12, T1p) to the signal input (SE) and via a second transfer transistor (T21, T22, T2p) to the associated voltage divider tap of the voltage divider as applied to the reference voltage (Ur). Moreover, each inverting comparator input (-), via capacitor (C1, C2, Cp) is applied to the associated voltage divider tap and, via a third transfer transistor (T31, T32, T3p) and across a resistor (R'1, R'2, R'p) arranged in series therewith, to the associated comparator output. The second and third transfer transistors are rendered conductive during short intervals (T) between conversions by the clock signal (F), and the first transfer transistors are rendered non-conductive via the inverter (IV), and during the conversion time (t) the first transfer transistors are rendered conductive, and the second and third transfer transistors are rendered non-conductive.

Abstract: An analog-to-digital converter for cameras generates a digital output signal representing the difference between a pair of analog input signals by converting a generated variable digital signal into a variable analog signal, combining a first analog input signal with the variable analog signal to provide a calculated analog signal and comparing the calculated analog signal with a second analog input signal to determine whether or not such signals have a predetermined relationship with respect to one another such that the variable digital signal is fixed when the aforementioned predetermined relationship is determined to exist.

Abstract: A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.

Abstract: An analog-to-digital converting circuit comprises an input, a clock signal circuit providing first and second clock signals having the same frequency but having a half-cycle phase difference therebetween; first and second analog-to-digital converting stages each having an input coupled to the converting circuit input for receiving an input analog signal, a control terminal for receiving a respective one of the first and second control clock signals, and an output providing an N-bit binary-coded digital signal representing the level of the input analog signal, each having a voltage quantizing interval of .DELTA.V; an output terminal; and a multiplexing circuit, such as a parallel-to-serial converter, for alternately applying to the output terminal the binary coded digital signals of the first and the second analog-to-digital converting stages.

Abstract: Coding and decoding method and apparatus are disclosed for implementation of a novel truncated Huffman type code using different length code words. Input signals to be encoded have different probabilities of occurance, and the most frequently occuring signals are assigned the shortest code words. Infrequently occuring input signals are labelled using one of the code words. The set of different length code words employed in the invention include a single binary 1 bit at the least significant bit position of each of the code words. Decoding simply includes means for counting the number of binary 0 bits between the 1 bits of the code word stream.

Abstract: A precision digital random data generator comprising a matched pair of D-type flip-flops, a differential amplifier for comparing integrated outputs of the flip-flops, provisions for a noisy analog input of the general type (n)t feeding one input of the comparator with the output of the comparator feeding a D input of one of the D type flip-flops which generates an output which statistically correlates with the analog input and is also fed to the other input of the comparator.

Abstract: A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.

Abstract: A method and a device for coding binary data to be transmitted and a device for decoding coded data dispense with the need to transmit a direct-current component and make it possible to reconstitute clock signals from coded data without any addition of a particular channel. With this objective, the input signal constituted by a sequence of groups of eight binary data is converted to a coded signal constituted by a sequence of words of sixteen binary data associated respectively with the groups and having a data repetition frequency which is double the repetition frequency of the input signal data. The words are also chosen so as to ensure that each datum of the coded signal is followed or preceded by a datum having the same logic state. Furthermore, a sequence of particular words is inserted at the beginning of the message in order to permit easy recovery of clock signals at the time of decoding.

Abstract: A telephone transmission circuit for connection to telephone line terminals includes a transmitter amplifier, a receiver amplifier and a balancing circuit for suppressing the leakage of the output of the transmitter amplifier to the receiver amplifier, the transmitter amplifier being connected to the line terminals so that a power supplied from the line is effectively used. Good impedance matching between the line and the telephone transmission circuit is achieved by the automatic adjustment of the balancing circuit responsive to the line length between the telephone transmission circuit and an exchange.

Abstract: In a parallel analog-to-digital converter wherein the comparator inputs are switched between +1/2 the voltage corresponding to the least significant bit and -1/2 said voltage. There is provided a bipolar differential amplifier-like circuit with a resistor connecting the collectors of the two transistors and a constant current source disposed in the emitter circuit. The comparator inputs are provided with the analog signal through said resistor, while the base of one of said transistors is provided with a clock signal having one-half the frequency of the converter clock signal.

Abstract: A semiconductor circuit having an improved current switching function is disclosed. The circuit comprises at least one current switch unit including a current source, a current output node, a field effect transistor connected between the current output node and the current source, an inverting amplifier having an output supplied to a gate of the field effect transistor and an input connected to the junction point of the current source and the field effect transistor and means for controlling operation of the amplifier.

Abstract: A compandor converts a linear code signal consisting of a polarity bit and a plurality of absolute value bits. The polarity bit represents the polarity of each sample value of an original analog signal. The absolute value bits represent the absolute value of the sample. The compandor converts the linear code into a nonlinear code including the polarity bit, a plurality of segment bits representing the segments in a characteristic curve to which the original analog signal belongs, and mantissa bits which indicate the position of the sample value in that segment.

Abstract: This analog-ditigal coder determines the coefficients a.sub.o . . . a.sub.n in two stages:during the first stage, the generator processes voltages V.sub.R and V.sub.Ri with i=1 to k-1;during the second stage, the generator processes the voltages V.sub.R and V.sub.Ri with i=1 to n-k.A capacitive voltage divider (2.sup.k C, C) preceded by two sample and hold means (S.sub.3, C.sub.3, S.sub.4, C.sub.4) assures the division by 2.sup.k of the voltages processed during the second stage and their summation with the final voltage V.sub.R(k-1) produced during the first stage.

Abstract: A signal-to-noise improving system is described which comprises a circuit input for incoming noisy analogue signals and a circuit output for digitally stored input signals which have an improved signal-to-noise ratio provided by the system and which have been reconverted to analogue form,said circuit input and said circuit output being connected to inputs of an analogue comparator arranged to give an output which signifies that the stored signal is either higher or lower in magnitude than the incoming signal or that the incoming signal is either higher or lower in magnitude than the stored signal,said comparator output being connected to a signal incrementor which is arranged to give a signal output which is the stored digital signal incremented higher or lower by a number digitally in response to either a higher or lower signal output from said comparator,a store for storing in digital from the so incremented input signals, the store output being connected to a digital to analogue converter 1 the output of w

Abstract: A digital to analog converter utilizes a digital missing pulse detector as a time interval measuring means in which the detector includes a programmable counter, the count of which is set to correspond with the digital number or word to be converted. Clock pulses at a high frequency are applied to advance the programmable counter from a reset condition to a terminal or output condition, and the time interval produced depends upon the binary word or number set into the programmable counter. Pulses at a second lower frequency, equal to the repetition rate of the system, are applied to the input of the time interval measuring circuit; so that the output is a series of pulse width modulated pulses having a duty cycle corresponding to the binary word originally set into the programmable counter.