Abstract: A parallel to serial converter is described for recording channel applications, wherein a coded symbol comprising a plural number of bits is to be rotated or converted to a serial stream. The converter includes a variable delay section which accepts the parallel code inputs on a plurality of lines and delays each input bit a predetermined number of counts, depending upon which line it is input on. The delay unit supplies a selector array of gates with bit signals, and the selector array reorders the bits into the desired serial stream. An output register is provided to reclock the serial stream prior to further channel processing.

Abstract: A method and apparatus for encoding or decoding data in accordance with a coding format, referred to herein as Y.phi. and which is based on the 3PM coding format. Data encoded in accordance with the Y.phi. format is generated by initially encoding, at a prearranged clocking frequency, binary data in accordance with 3PM format, applying such encoded data to one input terminal of an exclusive OR gate and applying clocking pulses, at the prearranged frequency to the other input terminal. Decoding is similarly achieved by passing the encoded data through an exclusive OR gate. Data encoded according to the Y.phi. format is particularly advantageous on account of the relatively high density of flux transitions which it generates, which may be desirable in certain circumstances particularly if both high and low rate data is to be encoded on the same magnetic tape.

Abstract: A circuit for compacting variable length data words into a fixed word length format is disclosed. Each variable length data word and its associated leading 0's are separated by a delimiter bit and stored in memory. When the memory is accessed, the output word is loaded in parallel into a first shift register and shifted to strip the leading 0's and delimiter bit. The remaining data bits are then shifted serially into a second shift register. When the second shift register is full, the resultant fixed length data word is latched out. When the first shift register is empty, the next word is loaded in from memory. In this way, a series of variable length words may be compacted into a series of fixed length words. This circuit is useful for compacting variable length Huffman codes since the boundaries between codes are self evident. This circuit can also be used as a character generator, where the variable length data output comprises the bits required to generate a character image on a raster scanned display.

Abstract: A very fast BCD-to-binary converter useful for addressing a digital memory. The converter includes a logical level comprised of at least three specially chosen AND-OR-INVERT integrated circuit gates, having at least five inputs, for producing binary output signals representing bits of the converted binary number.

Abstract: The present invention is a speech module including a central processing unit, a memory, a continuously variable slope delta demodulator, and related filter, amplifier, and speaker circuits connected to a master controller in a reproduction machine. Upon sensing certain machine conditions, the master controller provides suitable signals to the voice response module. In response, the voice response module locates starting addresses and lengths of words and phrases and reproduces the appropriate response. In one embodiment, the speech module is connected to a shared line communication system.

Abstract: An apparatus and method for encoding information receiving a binary information stream. The apparatus actuates one of four outputs as determined by the last output actuated and the binary level of the binary bit received.

Abstract: In a data encoding system, digital data is encoded by adjusting the time position of each transition of a rectangular waveform with respect to the immediately preceding transition and in dependence on the value of the data units to be encoded. In one example disclosed, each data unit is a pair of bits of digital data which can therefore have any one of four binary values: 11, 10, 01 or 00. Immediately after a previous transition (T1), the system encodes the next pair of bits and makes the next transition at a time position (T2) dependent on the value of these bits. If the bits are 00, the next transition T2 is spaced from T1 by eight clock periods. If the bits are 01, T2 can occur either seven or nine clock periods after T1. If the bits are 10, T2 can occur either six or ten clock periods after T1. Finally, if the bits are 11, then T2 can occur either five or eleven clock periods after T1.

Abstract: An input analog signal, such as a sound signal, is sampled by a sample-and-hold circuit, while sampling timing is variable in accordance with the amplitude variation of the analog signal. A difference between the amplitude of the analog signal and the amplitude of the output signal of the sample-and-hold circuit is detected, and the detected difference is integrated after passing through a square-law detecter. On the other hand, the average amplitude level of the input analog signal is detected to be compared with the integrated value. The sampling timing will be determined in accordance with the result of the comparison so that frequency of sampling pulses applied to the sample-and-hold circuit varies in accordance with the waveform of the input analog signal. The interval between two adjacent sampling pulses may be detected and stored together with digitally coded signals indicative of varying amplitudes of the input analog signal for recording or writing the analog signal information in a memory.

Abstract: A PCM encoder for converting a voice signal into a eight-bit code by approximating the .mu.-low characteristic where .mu.=255 with 15 segments comprises a capacitor array circuit including eight capacitors for determining lowermost voltages of the segments, a resistor string circuit for producing step voltage in each of the segments, a comparator circuit for comparing the output voltage of the capacitor array circuit with a reference voltage, and a successive approximation register circuit for controlling switch groups provided in the capacitor array circuit and the resistor string circuit. The resistor string circuit is provided with taps for deriving voltages corresponding to (2n-1)/33 (where n=1-16) of a voltage applied across the resistor string. A PCM encoder which conforms to the .mu.-low with high fidelity and is capable of quantizing mid-tread at the first segment is disclosed.

Abstract: The enciphering section of an enciphering/deciphering system includes a random number generator, a primary code memory and a multiplex unit in addition to the actual enciphering unit. The deciphering section includes a deciphering unit, a primary code memory and a demultiplex unit. At the beginning of each transmission, and after disturbances, the enciphering and deciphering sections are first synchronized by means of a synchronization sequence. Then a random address is produced by the random number generator for a primary code, and a randomly determined auxiliary code is also selected. The address and the auxiliary code are then transmitted and the primary and auxiliary codes are loaded into the enciphering and deciphering units. The randomly controlled, statistical selection of the primary code simplifies the code management and thus the operation of the system.

Abstract: An analog-to-digital converter comprising a capacitive element for storing an analog input signal, a discharge means for discharging the charge stored in said capacitive element, a means for counting the number of clockpulses between the time of discharge starting and the time at which the voltage at the output of said capacitive element reaches a certain detection level, and a bias voltage supply means for supplying a bias voltage in order to bring the voltage at the output terminal of said capacitive element at the discharge starting time above said detection level.

Abstract: A signal processing apparatus includes an updown counter for storing a maximum value of analog video signals produced from an array of photoelectric converting elements in a form of digital signal, and a distortion memory for storing a distortion characteristic of the analog video signal output from the photoelectric converting element. A reference voltage is produced on the basis of the output voltages from the up-down counter and the distortion memory to be compared with the analog video signal output from the photoelectric converting element array for encoding the analog video signal into a corresponding binary signal. The up-down counter is decremented with a periodical interval.

Abstract: A system for converting analog torquer current to digital form is based on a current-controlled oscillator, preferably a YIG-tuned microwave oscillator, which produces an output frequency characterized by a nominally constant bias frequency term subject to drift and a tuning frequency term proportional to input current. An automatic calibration circuit gates the input current ON and OFF at a relatively low constant sampling rate. The number of cycles of the high frequency oscillator output is counted separately for the ON and OFF periods. The difference between the ON and OFF period counts is proportional to the input current and independent of the bias frequency. The system is specifically designed for converting analog torquer currents in inertial instruments to computer-compatible form.

Abstract: A companding analog to digital converter for converting an analog signal into a variable length multi-bit binary word, the number of said bits being a function of the magnitude of the analog signal being converted relative to the high end of the range of magnitudes capable of being converted. The analog signal is temporarily stored and is attenuated by a predetermined amount. The attenuated signal is converted into a multi-bit digital word. A group of the most significant bits of said digital word are examined to alter the attenuation of the stored analog signal dependent upon its magnitude relative to the full scale. The attenuated analog signal is again converted into a multi-bit digital word which is temporarily stored. The group of binary bits initially stored together with results of the second conversion operation are combined to develop a multi-bit digital word whose bit length is a function of the magnitude of the stored analog signal relative to scale.

Abstract: Method and apparatus for sequentially scanning a plurality of target elements with an electron scanning beam modulated in accordance with variations in a high-frequency analog signal to provide discrete analog signal samples representative of successive portions of the analog signal; coupling the discrete analog signal samples from each of the target elements to a different one of a plurality of high speed storage devices; converting the discrete analog signal samples to equivalent digital signals; and storing the digital signals in a digital memory unit for subsequent measurement or display.

Abstract: A multiposition switch is connected to two input data buses which buses can apply binary digital signals of two operands to the switch at one time. An output data bus is also connected to the switch. Depending upon the position of the switch, bits from one or both of the operands as well as bits from other sources are applied by the switch to the output bus so that the format of the operand on the output bus has a predetermined relationship to the operands on the input buses.

Abstract: A calibration apparatus for analog-to-digital converter or transient recorder including both analog and digital sections is disclosed. A built-in calibrator automatically calibrates the gain and DC level of the entire system to substantially the same accuracy as that of the digital section, thereby avoiding relatively large errors of the analog section. The amplitude or gain calibration is always performed over the full range of the digitizer used in the digital section.

Abstract: A position encoder for providing signals that reflect the position of an object is contained in a housing which can be rotated back and forth to update the encoder. The encoder comprises a sun gear and a planet gear, and these gears are connected to an object. From the rotation of these gears, those signals that reflect the position of the object are generated. Rotating the case causes the gears to rotate relative to each other and to sensors which produce the signals. By rotating the case back and forth between reference and update positions, those signals are generated and the encoder is thereby updated without moving the object.

Abstract: A digitally controlled, presettable, ramp signal generating arrangement comprising digital to analogue converter means (DA) and integrator means (A1, A2) having a first mode in which its output (0) assumes a value representative of the output of the converter means, and a second mode in which its output changes at a rate dependent on the output of the converter means. The arrangement finds especial application in symbol display arrangements.

Abstract: An absolute-incremental hybrid shaft position encoder providing compacted high resolution. In the preferred embodiment an encoder track is superimposed by a shutter so as to make multiple track revolutions appear electrically as a single revolution.