Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.

Abstract: A method of manufacturing a semiconductor device includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a substrate, forming a memory opening through the stack, forming a layer stack including a memory material layer, a tunneling dielectric layer, and a first semiconductor material layer in the memory opening, forming a protective layer over the first semiconductor channel layer, physically exposing a semiconductor surface underneath the layer stack by anisotropically etching horizontal portions of the protective layer and the layer stack at a bottom portion of the memory opening, removing a remaining portion of the protective layer selective to the first semiconductor channel layer, and forming a second semiconductor channel layer on the first semiconductor channel layer.

Abstract: A plasma stabilization method and a deposition method using the same are disclosed. The plasma stabilization method includes (a) supplying a source gas and (b) supplying a purge gas. The method may also include (c) supplying a reactive gas and (d) supplying plasma. The purge gas and the reactive gas are continuously supplied into a reactor during (a) through (d), and the plasma stabilization method is performed in a state where no substrate exists in the reactor.

Abstract: According to the embodiment, a substrate treating device 10 for treating a semiconductor wafer W using an etchant L containing hydrofluoric acid and nitric acid includes a storage tank 210 that stores the etchant L; a concentration sensor 256 that measures a concentration of nitrous acid in the etchant L; an alcohol feeding line 280 that feeds IPA to the etchant L and maintains the concentration of nitrous acid to a predetermined value or more; and a substrate treating unit 100 that feeds the etchant L in the storage tank 210 to the semiconductor wafer W. The substrate treating device can improve the etching efficiency by efficiently generating nitrous acid, and thereby producing an etchant having a nitrous acid concentration suitable for etching.

Abstract: A method of manufacturing a mask assembly includes forming, via an electroforming process, a base material including at least one opening on an electrode plate; and reprocessing the at least one opening using a laser to form at least one reprocessed opening.

Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.

Abstract: A power module is disclosed, including a power module substrate in which a circuit layer is arranged on one surface of an insulating layer; and a semiconductor element that is bonded onto the circuit layer, in which a copper layer composed of copper or a copper alloy is provided on a surface of the circuit layer to be bonded to the semiconductor element, a solder layer formed by using a solder material between the circuit layer and the semiconductor element is provided, an alloy layer containing Sn as a main component, 0.5% by mass or more and 10% by mass or less of Ni, and 30% by mass or more and 40% by mass or less of Cu at an interface of the solder layer with the circuit layer is formed, and the coverage of the alloy layer at the interface is 85% or more.

Abstract: A sensing apparatus for sensing target materials including biological or chemical molecules in a fluid. One such apparatus includes a semiconductor-on-insulator (SOI) structure having an electrically-insulating layer, a fluidic channel supported by the SOI structure and configured and arranged to receive and pass a fluid including the target materials, and a semiconductor device including at least three electrically-contiguous semiconductor regions doped to exhibit a common polarity. The semiconductor regions include a sandwiched region sandwiched between two of the other semiconductor regions, and configured and arranged adjacent to the fluidic channel with a surface directed toward the fluidic channel for coupling to the target materials in the fluidic channel, and further arranged for responding to a bias voltage. The sensing apparatus also includes an amplification circuit in or on the SOI and that is arranged to facilitate sensing of the target material near the fluidic channel.

Abstract: An environmentally green wet etch process for selective removal of cobalt metal generally includes applying water that is free of added buffers, acids, and/or bases to a substrate including exposed cobalt metal. The process can be utilized to form recesses where desired such as may be implemented for metal contact fill, metal gate fill, interconnect fill, or the like.

Abstract: A temporary bonding arrangement for wafer processing is provided comprising a first temporary bond layer (A) of thermoplastic resin, a second temporary bond layer (B) of thermosetting siloxane polymer, and a third temporary bond layer (C) of thermosetting polymer. Layer (B) is cured with a curing catalyst contained in layer (A) which is laid contiguous to layer (B). An adhesive layer of uniform thickness is formed without insufficient step coverage and other failures.

Abstract: A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film.

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.

Abstract: In various embodiments, evaporation sources for deposition systems are heated and/or cooled via a fluid-based thermal management system.

Abstract: An object of the present invention is to provide an organic semiconductor composition, which improves the insulation reliability of an organic thin-film transistor without greatly reducing the mobility of the organic thin-film transistor, an organic thin-film transistor which is prepared by using the organic semiconductor composition, and electronic paper and a display device which use the organic thin-film transistor. The organic semiconductor composition of the present invention contains an organic semiconductor material (A) and a polymer compound (B) containing a repeating unit represented by the following Formula (B).

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52?) with ion doping process, and the oxide conductor layer (52?) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

Abstract: The inventive concepts provide semiconductor devices and methods for manufacturing the same in which the method includes forming a capacitor including a bottom electrode, a dielectric layer and a top electrode sequentially stacked on a substrate, and also where formation of the top electrode includes forming a first metal nitride layer on the dielectric layer, and forming a second metal nitride layer on the first metal nitride layer, in which the first metal nitride layer is disposed between the dielectric layer and the second metal nitride layer, and the first metal nitride layer is formed at a temperature lower than a temperature at which the second metal nitride layer is formed.

Abstract: A method and composition for producing a porous low k dielectric film via chemical vapor deposition is provided. In one aspect, the method comprises the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising an alkyl-alkoxysilacyclic compound, and a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 2.7 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of diagonal shorts and/or leakages.

Abstract: A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel layer that is formed at a position on the first insulating film overlapping the gate electrode and formed of an oxide semiconductor, a second insulating film formed on the channel layer, and a third insulating film formed so as to cover the second insulating film. A source electrode and a drain electrode are formed on the third insulating film. Each of the source electrode and the drain electrode is connected to the channel layer through the corresponding one of contact holes penetrating the second insulating film and the third insulating film.

Abstract: According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.