Patents Examined by Caleen Sullivan
  • Patent number: 10062679
    Abstract: Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Michel Koopmans
  • Patent number: 10062627
    Abstract: According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the semiconductor chips, and a film covering at least an upper surface of the sealing resin layer, the film made from a material selected from the group consisting of zinc, aluminum, manganese, alloys thereof, metal oxides, metal nitrides, and metal oxynitrides.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masaji Iwamoto
  • Patent number: 10056350
    Abstract: The method of fabricating a fan-out package structure comprises: S1, providing a substrate (1), forming an adhesive layer (2) on the substrate's upper surface; S2, forming a redistribution layer (3) on the adhesive layer's upper surface; S3, bonding one first chip (4) to the redistribution layer's upper surface, and constructing at least two first bump structures (5), wherein the first chip and the first bump structures are all electrically connected to the redistribution layer, and top portions of the first bump structures are taller than a top portion of the first chip; S4, forming a plastic encapsulation layer (6) on the upper surface of the redistribution layer, wherein the plastic encapsulation layer embeds the first chip and exposes upper ends of the first bump structures; and S5, removing the substrate and the adhesive layer, and constructing a second bump structure (7) on a lower surface of the redistribution layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 21, 2018
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Chengchung Lin, Qifeng Cai
  • Patent number: 10050113
    Abstract: A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Oliver Blank, David Laforet, Cedric Ouvrard, Li Juin Yip
  • Patent number: 10050042
    Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang Chen, Kuo-Chiang Ting, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 10050112
    Abstract: A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm?3 and at most equal to 2*1018 cm?3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Erwan Morvan
  • Patent number: 10050137
    Abstract: A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventor: Erwan Morvan
  • Patent number: 10043705
    Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chang Chu, Yao-Wen Chang, Sheng-Chau Chen, Alexander Kalnitsky
  • Patent number: 10043728
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 7, 2018
    Assignee: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 10043819
    Abstract: A 3D memory device includes a plurality of vertical pillars composed of a vertical channel and a multilayer data storage structure. The multilayer data storage structure can comprise a dielectric charge trapping structure. A stack of dielectric lined conductive strips separated in the stack by insulating strips have sidewalls disposed adjacent the corresponding vertical pillars. The conductive strips have a dielectric liner having a dielectric constant ? greater than 7 on the sidewalls in contact with the outside layer of the multilayer data storage structure on the corresponding pillar. The conductive strips in embodiments described herein can comprise a relatively low resistance material, such as a metal or a metal nitride. A manufacturing method using Si—Ge selective etching of sacrificial layers can be used in a gate replacement process to form the dielectric conductive strips.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: August 7, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10043975
    Abstract: [Problem] To provide a technology that allows a film or glass to be bonded to a transport substrate and to be easily separated during the manufacture of a substrate. [Solution] Provided is a method for manufacturing a substrate having an electronic device formed on a surface, the method comprising a formation step for forming an inorganic material layer on at least one of a bonding surface by which the substrate having an electronic device formed on a surface is to be bonded to a transport substrate, and a bonding surface on the transport substrate for transporting the substrate; a bonding step for pressing the substrate and the transport substrate against each other and bonding the substrate and the transport substrate by the inorganic material layer; and a separation step for separating the substrate and the transport substrate.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 7, 2018
    Assignee: LAN TECHNICAL SERVICE CO., LTD.
    Inventors: Tadatomo Suga, Yoshiie Matsumoto
  • Patent number: 10032932
    Abstract: Disclosed are an oxide thin-film transistor and a method of fabricating the same. The oxide thin-film transistor according to an embodiment of the present disclosure includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; and an oxide thin film formed on the gate insulating layer, wherein the oxide thin film include a channel region, source region and drain regions disposed on the channel region and spaced apart from each other, and a concentration profile due to a dopant diffused from the gate insulating layer, wherein the channel region operates as a channel layer by the concentration profile.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: July 24, 2018
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyun Jae Kim, Jae Won Na
  • Patent number: 10032629
    Abstract: A method of manufacturing a semiconductor device includes: providing a substrate; and forming a film on the substrate by supplying a silicon hydride and a halogen element-free catalyst containing one of a group III element or a group V element to the substrate, under a condition that the silicon hydride is not thermally decomposed when the silicon hydride is present alone.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 24, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takafumi Nitta, Satoshi Shimamoto, Yoshiro Hirose
  • Patent number: 10020196
    Abstract: Techniques disclosed herein provide a method and fabrication structure for pitch reduction for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A pattern of alternating materials is formed on an underlying layer. An etch mask is positioned on the pattern of alternating materials. One or more of the alternating materials can be preferentially removed relative to other materials to uncover a portion of the underlying layer. The etch mask and the remaining lines of alternating material together form a combined etch mask defining sub-resolution features.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 10, 2018
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10020343
    Abstract: Systems and methods may be provided for fabricating infrared focal plane arrays. The methods include providing a device wafer, applying a coating to the device wafer, mounting the device wafer to a first carrier wafer, thinning the device wafer while the device wafer is mounted to the first carrier wafer, releasing the device wafer from the first carrier wafer, singulating the device wafer into individual dies, each die having an infrared focal plane array, and hybridizing the individual dies to a read out integrated circuit.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 10, 2018
    Assignee: FLIR Systems, Inc.
    Inventors: Edward K. Huang, Andrew D. Hood, Bryan Gall, Paula Heu, Richard E. Bornfreund
  • Patent number: 10020293
    Abstract: The present invention discloses a transferring method, a manufacturing method, a device and an electronic apparatus of micro-LED. The method for transferring micro-LED comprises: forming a micro-LED on a laser-transparent original substrate; bringing the micro-LED into contact with a pad preset on a receiving substrate; and irradiating the original substrate with laser from the original substrate side to lift-off the micro-LED from the original substrate.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: July 10, 2018
    Assignee: GoerTek Inc.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 10020377
    Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: July 10, 2018
    Assignee: Pragmatic Printing Limited
    Inventors: John James Gregory, Richard David Price
  • Patent number: 10020420
    Abstract: A repairing method, manufacturing method, device and electronic apparatus of micro-LED are disclosed. The method for repairing micro-LED defects comprises: obtaining a micro-LED defect pattern on a receiving substrate; forming micro-LEDs (703b) corresponding to the defect pattern on a laser-transparent repair carrier substrate (707); aligning the micro-LEDs (703b) on the repair carrier substrate (707) with defect positions on the receiving substrate, and bringing the micro-LEDs (703b) into contact with pads at the defect positions; and irradiating the repair carrier substrate with a laser from the repair carrier substrate side, to lift-off the micro-LEDs from the repair carrier substrate (707).
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 10, 2018
    Assignee: GoerTek Inc.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 10014445
    Abstract: A manufacturing method of a light-emitting device is disclosed. The method includes: providing a semiconductor wafer, including a substrate having a first surface and a second surface opposite to the first surface; and a semiconductor stack on the first surface; removing a portion of the semiconductor stack to form an exposed region; forming a first reflective structure on the exposed region; and providing a radiation on the second surface corresponding to a position of the first reflective structure.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 3, 2018
    Assignee: EPISTAR Corporation
    Inventors: Jar-Yu Wu, Chun-Lung Tseng, Ching-Hsing Shen, Wei-Ting Cheng, Jui-Fen Chien, Yu-Ming Kung, Chiao-Yao Cheng
  • Patent number: 10014231
    Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dong Seup Lee, Jungwoo Joh, Sameer Pendharkar