Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, includes a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, and a gate structure located on the second source layer. The semiconductor device also includes a source contact structure passing through the gate structure, the second source layer, and the first insulating passivation layer. The source contact structure is coupled to the first source layer.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: The present disclosure provides a pixel array and a display device. The pixel array includes first sub-pixels, second sub-pixels and third sub-pixels; the first sub-pixels and the third sub-pixels are alternately arranged along a first direction to form first pixel groups, and are alternately arranged along a second direction to form third pixel groups; the second sub-pixels are arranged along the first direction to form second pixel groups, and are arranged along the second direction to form fourth pixel groups; wherein the first pixel groups and the second pixel groups are alternately arranged in the second direction; the third pixel groups and the fourth pixel groups are alternately arranged along the first direction; wherein a shape of the second sub-pixel includes a polygon, a plurality of sides of the polygon include straight lines or arcs, and the shape of the second sub-pixel includes at most one symmetry axis.

Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Abstract: Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Abstract: The present disclosure provides a display substrate and a display device, wherein the display substrate includes a substrate body, the substrate body includes a plurality of island portions spaced apart from each other, a plurality of connection areas connecting the plurality of island portions, and a penetration portion penetrating the substrate body among the plurality of connection areas, at least a portion of each edge of the island portion is connected with the connection area; each island portion is respectively provided with a plurality of pixel groups, each pixel group includes a first pixel unit and a second pixel unit which are adjacently arranged along a first direction, an arrangement of the sub-pixels in the first pixel unit is different from an arrangement of the sub-pixels in the second pixel unit, the plurality of pixel groups form an n×m arrangement on the island portion and cover the whole island portion.

Abstract: Processes for continuous compositional grading for realization of low charge carrier barriers in electro-optical heterostructure semiconductor devices are provided. An example process includes forming, onto one or more semiconductor layers of an electro-optical semiconductor device, a first semiconductor layer associated with a first bandgap value and forming, onto the first semiconductor layer, a grading layer associated with a continuous compositional grading. The example method further includes forming, onto the grading layer, a second semiconductor layer associated with a second bandgap value. The second bandgap value is different than the first bandgap value.

Abstract: A transistor with an emitter, base, and collector. The base includes a monocrystalline base layer. A sacrificial material is formed on the monocrystalline base layer. The sacrificial material is removed to expose a portion of the monocrystalline base layer. A base silicide includes a portion formed on the portion of the base monocrystalline base layer that was exposed by the removal of the sacrificial material.

Abstract: Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.

Abstract: An semiconductor manufacturing apparatus and method to smooth surfaces of discrete pads on a substrate. The method includes placing a surface of one of the discrete pads in registration with a first chamber of a set of chambers of a smoothing tool, the set corresponding to a smoothing cycle of the smoothing tool; etching, within the first chamber, a surface of one of the discrete pads to form an etch layer on the surface; placing the surface in registration with a second chamber of the set; after the etch, pumping gas and vapor from the surface within the second chamber; placing the surface in registration with a third chamber of the set; and applying heating to the surface in the third chamber to smooth the surface.

Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided. The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film.

Abstract: Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma by top and side RF sources and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.

Abstract: An ionizing radiation detector includes a p-type semiconductor single crystal substrate having first and second major planar opposing surfaces, where the p-type semiconductor single crystal substrate is doped with n-type dopant atoms, and where a concentration of deep level acceptor defects is greater than a concentration of the n-type dopant atoms in the p-type semiconductor single crystal substrate; a cathode electrode on the first major planar opposing surface of the p-type semiconductor single crystal substrate, and a plurality of anode electrodes on the second major planar opposing surface of the p-type semiconductor single crystal substrate.

Abstract: An imaging device including: pixel area and a peripheral area that lies outside the pixel area; light receiving element provided in the pixel area; circuit board provided in the pixel area and the peripheral area, the circuit board including a semiconductor substrate and a multilayer wiring layer, the multilayer wiring layer being provided between the semiconductor substrate and the light receiving element; first wiring line provided in the multilayer wiring layer, the first wiring line being electrically coupled to the light receiving element; a protective member that is opposed to the circuit board, the protective member and the circuit board sandwiching the light receiving element; and an extended wiring section provided between the semiconductor substrate and the protective member in the peripheral area, one end of the extended wiring section being open and another end of the extended wiring section being electrically coupled to the first wiring line.

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: An image sensing device is provided to include a plurality of unit pixel regions arranged in a first direction and a second direction, a first device isolation region structured to isolate the plurality of unit pixel regions from each other, a plurality of photoelectric conversion regions in the substrate to form a plurality of imaging pixels structured to generate photocharges, a plurality of second device isolation regions configured to define active regions of the plurality of imaging pixels, a plurality of floating diffusion regions formed in a first active region to store the photocharges, and a plurality of transfer gates structured to transmit the photocharges. The floating diffusion region is located contiguous to the transfer gate in the first direction and the second direction and is structured to surround a plurality of side surfaces of a corresponding transfer gate.

Abstract: An electro-optically controlled active-matrix system comprises a system substrate, row wires extending in a row direction disposed on the system substrate, a row controller providing a row electrical signal to each row wire, column light-pipes extending in a column direction disposed on the system substrate, a column controller providing a column optical signal to each column light-pipe, and pixels disposed over the system substrate. Each pixel can comprise a pixel circuit that is uniquely responsive to a row wire and to a column light-pipe, the pixel circuit receiving the row electrical signal from the row wire and receiving the column optical signal from the column light-pipe. In some embodiments, column wires carrying column electrical signals extend in a column direction over the system substrate and the pixel circuit is capacitively coupled to the row wire, the column wire, or both.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.