Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A disclosed transistor structure includes a gate electrode, an active layer, a source electrode, a drain electrode, an insulating layer separating the gate electrode from the active layer, and a carrier modification device that reduces short channel effects by reducing carrier concentration variations in the active layer. The carrier modification device may include a capping layer in contact with the active layer that acts to increase a carrier concentration in the active layer. Alternatively, the carrier modification device may include a first injection layer in contact with the source electrode and the active layer separating the source electrode from the active layer, and a second injection layer in contact with the drain electrode and the active layer separating the drain electrode from the active layer. The first and second injection layers may act to reduce a carrier concentration within the active layer near the source electrode and the drain electrode.

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: An optical modulator includes an emitter layer with N-type doping having a first bandgap energy; a base layer with P-type doping having a second bandgap energy; a sub-emitter layer disposed between the emitter layer and the base layer, wherein the sub-emitter layer has a third bandgap energy that is less than both the first bandgap energy and the second bandgap energy. The sub-emitter layer provides a barrier to electrons flowing from the emitter layer, while allowing photo-generated holes to recombine in the sub-emitter layer thereby mitigating current amplification.

Abstract: A display device includes a first display area including a plurality of first pixel electrodes, and a second display area including a plurality of second pixel electrodes. A first pitch in a first direction of the plurality of first pixel electrodes is smaller than a second pitch in the first direction of the plurality of second pixel electrodes, and a length in the first direction of the first pixel electrodes is smaller than a length in the first direction of the second pixel electrode.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.

Abstract: A semiconductor light-receiving element, includes: a semiconductor substrate; a high-concentration layer of a first conductivity type formed on the semiconductor substrate; a low-concentration layer of the first conductivity type formed on the high-concentration layer of the first conductivity type and in contact with the high-concentration layer of the first conductivity type; a low-concentration layer of a second conductivity type configured to form a PN junction interface together with the low-concentration layer of the first conductivity type; and a high-concentration layer of the second conductivity type formed on the low-concentration layer of the second conductivity type and in contact with the low-concentration layer of the second conductivity type. The low-concentration layers have a carrier concentration of less than 1×1016/cm3. The high-concentration layers have a carrier concentration of 1×1017/cm3 or more.

Abstract: A display device includes a first display area including a plurality of first pixel electrodes, and a second display area including a plurality of second pixel electrodes. A first pitch in a first direction of the plurality of first pixel electrodes is smaller than a second pitch in the first direction of the plurality of second pixel electrodes, and a length in the first direction of the first pixel electrodes is smaller than a length in the first direction of the second pixel electrode.

Abstract: Germanium (Ge)-Silicon (Si) structures, optoelectronic devices and method for forming same. A structure comprises a Si substrate, a Ge seed layer and a Ge epitaxial layer separated by respective interfaces that share a common plane normal, wherein the Si substrate and the Ge seed layer have a same first doping type with a first doping level, and a locally doped region formed in the Si layer adjacent to the Ge seed layer and having a second doping type with a second doping level, wherein the locally doped region is designed to reduce leakage currents between the Si substrate and the Ge epitaxial layer when an electrical bias is applied to the structure.

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.

Abstract: Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.

Abstract: A photosensitive transistor is disclosed herein that includes: a semiconductor substrate of the first conductivity type as a collector layer; above it a less doped layer of the first conductivity type having regions of different thickness; a semiconductor base layer of the second conductivity type above at least parts of the regions of the less doped layer; and an emitter layer of the first conductivity type above at least parts of the base layer, but not above at least one part of the part of the base layer disposed above the thinner region of the less doped layer.

Abstract: Gate cutting techniques for integrated circuit devices, particularly for fin-like field effect transistor devices, are disclosed herein. An exemplary method includes receiving an integrated circuit device that includes a gate structure and performing a gate cut process to separate the gate structure into a first gate structure and a second gate structure. The gate cut process includes selectively removing a portion of the gate structure, such that a residual gate dielectric layer extends between the first gate structure and the second gate structure. In some implementations, the residual gate dielectric includes a high-k dielectric material. The method further includes forming a gate isolation region between the first gate structure and the second gate structure.

Abstract: Provided is a terahertz light source device including an antenna, a plurality of wire electrodes configured to connect the antenna to a power source, a capacitor connected to the wire electrodes between the antenna and the power source, and a plurality of resonance tunneling diodes connected to the wire electrodes between the capacitor and the antenna, and configured to generate a terahertz wave by coupling with the capacitor as a parallel resonance circuit with respect to the power source.

Abstract: According to embodiments provided herein, the performance of photovoltaic device can be improved by rapidly heating an absorber layer of a device in open-circuit to a high temperature for a short period of time followed by rapid quenching. The rapid heating may be accomplished by one or more pulses of high intensity electromagnetic energy. The energy may be visible light. The energy may be absorbed primarily in the absorber layer, such that the absorber layer is preferentially heated, promoting chemical reactions of dopant complexes. The dopant chemical reactions disrupt compensating defect complexes that have formed in the device, and regenerate active carriers.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.