Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

Abstract: According to an embodiment, a self-powered sensor comprises at least one first layer emitting light in a preset wavelength band by receiving power from an outside, or receiving the emitted light reflected by an object, at least one second layer receiving light and generating a current, and a plurality of connectors each grown between two adjacent ones of the at least one first layer and the at least one second layer, the plurality of connectors transferring the generated current to the outside or transferring the power received from the outside to the at least one first layer and the at least one second layer.

Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer may be formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.

Abstract: The present technology relates to a light reception device and a distance measurement module whose characteristic can be improved. The light reception device includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer. The semiconductor layer includes a first tap having a first voltage application portion and a first charge detection portion arranged around the first voltage application portion, and a second tap having a second voltage application portion and a second charge detection portion arranged around the second voltage application portion. Furthermore, the light reception device is configured such that a phase difference is detected using signals detected by the first tap and the second tap. The present technology can be applied, for example, to a light reception device that generates distance information, for example, by a ToF method, and so forth.

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, a first insulative material vertically overlying the staircase structure, conductive contact structures comprising a conductive material extending through the first insulative material and in contact with the steps of the staircase structure, and a second insulative material extending in a first horizontal direction between horizontally neighboring conductive contact structures and exhibiting one or more different properties than the first insulative material. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: The present disclosure provides an OLED display panel and an OLED display device, and belongs to the field of display technology. The OLED display panel of the present disclosure includes a base substrate and a display cover disposed opposite to each other; a polarizing layer disposed between the base substrate and the display cover; a light extraction layer disposed between the base substrate and the display cover; the OLED display panel is provided with a light exit surface, and the light extraction layer is closer to the light exit surface than the polarizing layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

Abstract: Photodetectors using photonic crystals (PhCs) in polysilicon film that include an in-plane resonant defect. A biatomic photodetector includes an optical defect mode that is confined from all directions in the plane of the PhC by the photonic bandgap structure. The coupling of the resonance (or defect) mode to out-of-plane radiation can be adjusted by the design of the defect. Further, a “guided-mode resonance” (GMR) photodetector provides in-plane resonance through a second-order grating effect in the PhC. Absorption of an illumination field can be enhanced through this resonance.

Abstract: A stacked III-V semiconductor photonic device having a second metallic terminal contact layer at least formed in regions, a highly doped first semiconductor contact region of a first conductivity type, a very low doped absorption region of the first or second conductivity type having a layer thickness of 20 ?m-2000 ?m, a first metallic terminal contact layer, wherein the first semiconductor contact region extends into the absorption region in a trough shape, the second metallic terminal contact layer is integrally bonded to the first semiconductor contact region and the first metallic terminal contact layer is arranged below the absorption region. In addition, the stacked III-V semiconductor photonic device has a doped III-V semiconductor passivation layer of the first or second conductivity type, wherein the III-V semiconductor passivation layer is arranged at a first distance of at least 10 ?m to the first semiconductor contact region.

Abstract: According to one embodiment, a ceramic metal circuit board is a ceramic metal circuit board formed by bonding metal circuit plates to at least one surface of a ceramic substrate. At least one of the metal circuit plates has an area of not less than 100 mm2 and includes a concave portion having a depth of not less than 0.02 mm within a range of 1% to 70% of a surface of the at least one of the metal circuit plates. The concave portion is provided not less than 3 mm inside from an end of the metal circuit plate.

Abstract: Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.

Abstract: An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure wherein a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operatively coupled with the wafer.

Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.

Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.

Abstract: A carrier configured to be attached to a semiconductor substrate via a first surface comprises a continuous carbon structure defining a first surface of the carrier, and a reinforcing material constituting at least 2 vol-% of the carrier.

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

Abstract: Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration.

Abstract: The present technology relates to a solid state imaging sensor that is possible to suppress the reflection of incident light with a wide wavelength band. A reflectance adjusting layer is provided on the substrate in an incident direction of the incident light with respect to the substrate such as Si and configured to adjust reflection of the incident light on the substrate. The reflectance adjusting layer includes a first layer formed on the substrate and a second layer formed on the first layer. The first layer includes a concavo-convex structure provided on the substrate and a material which is filled into a concave portion of the concavo-convex structure and has a refractive index lower than that of the substrate, and the second layer includes a material having a refractive index lower than that of the first layer. It is possible to reduce the reflection on the substrate such as Si by using the principle of the interference of the thin film. Such a technology can be applied to solid state imaging sensors.

Abstract: A PCSS comprises a photoconductive semiconductor block that exhibits electrically-conductive behavior when exposed to light of a predetermined wavelength; two or more electrodes fixed to the photoconductive semiconductor block and connectable to a power supply; a resonance cavity enveloping the photoconductive semiconductor block, the resonance cavity having a reflective outer surface to trap light within the resonance cavity and the photoconductive semiconductor block, the resonance cavity having a window through the reflective outer surface to admit light of the predetermined wavelength, the resonance cavity being transmissive to light of the predetermined wavelength within the reflective outer surface; and a light source directed toward the photoconductive semiconductor block and through the window, and emitting light at the predetermined wavelength. The photoconductive semiconductor block may include Si, GaAs, GaN, AlN, SiC, and/or Ga2O3.

Abstract: A method, apparatus and system with an autonomic, self-healing polymer capable of slowing crack propagation within the polymer and slowing delamination at a material interface.