Patents Examined by Caridad M. Everhart
  • Patent number: 7935641
    Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Yeon-hee Kim, Jung-hyun Lee, Yong-young Park, Chang-soo Lee
  • Patent number: 7932521
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: April 26, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 7927986
    Abstract: A method of plasma doping includes providing a dopant gas comprising a dopant heavy halogenide compound gas to a plasma chamber. A plasma is formed in the plasma chamber with the dopant heavy halogenide compound gas and generates desired dopant ions and heavy fragments of precursor dopant molecule. A substrate in the plasma chamber is biased so that the desired dopant ions impact the substrate with a desired ion energy, thereby implanting the desired dopant ions and the heavy fragments of precursor dopant molecule into the substrate, wherein at least one of the ion energy and composition of the dopant heavy halogenide compound is chosen so that the implant profile in the substrate is substantially determined by the desired dopant ions.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: April 19, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, George D. Papasouliotis, Edwin Arevalo
  • Patent number: 7921805
    Abstract: A liquid injector is used to vaporize and inject a silicon precursor into a process chamber to form silicon-containing layers during a semiconductor fabrication process. The injector is connected to a source of silicon precursor, which preferably comprises liquid trisilane in a mixture with one or more dopant precursors. The mixture is metered as a liquid and delivered to the injector, where it is then vaporized and injected into the process chamber.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: April 12, 2011
    Assignee: ASM America, Inc.
    Inventors: Michael A. Todd, Ivo Raaijmakers
  • Patent number: 7915125
    Abstract: A method of manufacturing a semiconductor device is provided which comprises: forming a first gate insulating film and a second gate insulating film in an active region of a semiconductor substrate; introducing an impurity of a first conductivity type into a first site where a first body region is to be formed, the first site being disposed under the first gate insulating film in the active region; forming a gate electrode on each of the first gate insulating film and the second gate insulating film; and introducing an impurity of the first conductivity type into the first site and a second site where a second body region is to be formed, the second site being disposed under the second gate insulating film in the active region, to form the first body region and the second body region, respectively.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hidekazu Sato
  • Patent number: 7915610
    Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near the surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-kwan Ryu, Jun-seong Kim, Sang-yoon Lee, Euk-che Hwang, Tae-sang Kim, Jang-yeon Kwon, Kyung-bae Park, Kyung-seok Son, Ji-sim Jung
  • Patent number: 7910490
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: March 22, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 7906435
    Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyasu Nishiyama
  • Patent number: 7906363
    Abstract: A method of fabricating a semiconductor device having a three-dimensional stacked structure by stacking semiconductor circuit layers on a support substrate, including the steps of: forming a trench in a semiconductor substrate; filling inside the trench with a conductive material to form a conductive plug; forming an element or circuit in an inside or on a surface of the semiconductor substrate where the conductive plug was formed; covering the surface of the semiconductor substrate where the element or circuit was formed with a second insulating film; and fixing the semiconductor substrate to the support substrate or a remaining one of the semiconductor circuit layers by joining the second insulating film to the support substrate or the remaining one of the semiconductor circuit layers through a wiring structure; selectively removing the semiconductor substrate to expose the first insulating film; and selectively removing the first insulating film.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 15, 2011
    Assignee: ZyCube Co., Ltd.
    Inventor: Mitsumasa Koyanagi
  • Patent number: 7902076
    Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a porous film above a semiconductor substrate; forming an altered layer by applying alteration treatment to a first pattern region of the porous film up to a predetermined depth; forming a first concave portion by etching a second pattern region to a depth deeper than the predetermined depth, the second pattern region at least partially overlapping the first pattern region of the porous film having the altered layer formed therein; and forming a second concave portion by selectively removing the altered layer from the porous film after forming the first concave portion.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsubasa Imamura
  • Patent number: 7902048
    Abstract: A method of forming a phase change layer may include providing a bivalent first precursor having germanium (Ge), a second precursor having antimony (Sb), and a third precursor having tellurium (Te) onto a surface on which the phase change layer is to be formed. The phase change layer may be formed by CVD (e.g., MOCVD, cyclic-CVD) or ALD. The composition of the phase change layer may be varied by modifying the deposition pressure, deposition temperature, and/or supply rate of reaction gas. The deposition pressure may range from about 0.001-10 torr, the deposition temperature may range from about 150-350° C., and the supply rate of the reaction gas may range from about 0-1 slm. Additionally, the above phase change layer may be provided in a via hole and bounded by top and bottom electrodes to form a storage node.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-chul Shin, Jae-ho Lee, Youn-seon Kang
  • Patent number: 7897464
    Abstract: A method of manufacturing a semiconductor device including a buried insulating film formed in a bottom part of a trench and a buried-type gate electrode formed in the trench, the method including selectively forming an insulating film in the bottom part of the trench, forming a resist having an opening in a part that corresponds to a region where a device isolation insulating film is formed on a surface of a semiconductor substrate after forming the insulating film, and oxidizing the surface of the semiconductor substrate in the opening to form the device isolation insulating film.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: March 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Junji Umezaki
  • Patent number: 7897501
    Abstract: A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a gate stack overlying the semiconductor substrate; forming spacers each having a first inner spacer and a second outer spacer on sidewalls of the gate stack; forming a protective layer on sidewalls of the spacers, covering a part of the semiconductor substrate, wherein an etching selectivity of the protective layer is higher than that of the first inner spacer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: March 1, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Li Cheng, Sun-Jay Chang, Tung-Heng Hsieh, Yung-Shen Chen
  • Patent number: 7897966
    Abstract: For avoiding the metallic inner surface of a PECVD reactor to influence thickness uniformity and quality uniformity of a ?c-Si layer (19) deposited on a large-surface substrate, (15) before each substrate is single treated at least parts of the addressed wall are precoated with a dielectric layer (13).
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: March 1, 2011
    Assignee: Oerlikon Solar AG, Trubbach
    Inventors: Hai Tran Quoc, Jerome Villette
  • Patent number: 7892864
    Abstract: A charged particle beam irradiation method includes setting an observation region on a sample, the sample including an object pattern to be observed, and the observation region including the object pattern, setting an irradiation region on the sample, the irradiation region being to be irradiated with a charged particle beam, the irradiation region including the observation region and being larger than the observation region, setting a non-irradiation region in the irradiation region, the non-irradiation region failing to be irradiated with the charged particle beam, irradiating the irradiation region except the non-irradiation region with the charged particle beam, and irradiating the observation region with a charged particle beam after the irradiating the irradiation region except the non-irradiation region with the charged particle beam.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideaki Abe
  • Patent number: 7875479
    Abstract: The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: January 25, 2011
    Assignee: National Chiao Tung University
    Inventors: Jin-Chern Chiou, Chih-Wei Chang
  • Patent number: 7875510
    Abstract: A method for manufacturing a thin-film device includes forming a separation layer on a substrate, forming a support layer of mainly clay containing silicate mineral having a layered crystal structure on the separation layer, forming a thin-film functional member on the support layer, applying an energy to the separation layer to reduce the adhesion between the substrate and the support layer, and removing the substrate from the support layer and the thin-film functional member.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: January 25, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Katsuyoshi Onodera
  • Patent number: 7871913
    Abstract: A method for manufacturing a semiconductor device having a vertical transistor includes forming hard masks on a semiconductor substrate to expose portions of the semiconductor substrate. Then the exposed portions of the semiconductor substrate are etched to define grooves in the semiconductor substrate. A gate conductive layer is formed on the hard masks and surfaces of the grooves to a thickness that does not completely fill the grooves. A sacrificial layer is formed on the gate conductive layer to completely fill the grooves. A partial thickness of the sacrificial layer is removed to expose the gate conductive layer and portions of the gate conductive layer formed on the hard masks and on sidewalls of upper portions of the grooves are removed. The remaining sacrificial layer is completely removed. Gates are formed on sidewalls of lower portions of the grooves by etching the gate conductive layer.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong Han Shin, Hyung Soon Park, Jum Yong Park, Sung Jun Kim
  • Patent number: 7871938
    Abstract: Disclosed is a producing method of a semiconductor device produced by transferring a plurality of substrates into a processing chamber, supplying oxygen-containing gas and hydrogen-containing gas into the processing chamber which is in a heated state to process the plurality of substrates by oxidation, and transferring the plurality of the oxidation-processed substrates out from the processing chamber, wherein the hydrogen-containing gas is supplied from a plurality of locations of a region corresponding to a substrate arrangement region in which the plurality of substrates are arranged in the processing chamber.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 18, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Takashi Ozaki, Kazuhiro Yuasa, Kiyohiko Maeda
  • Patent number: 7867904
    Abstract: A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: January 11, 2011
    Assignee: Intermolecular, Inc.
    Inventors: Tony P Chiang, Richard R Endo, James Tsung