Patents Examined by Carl W. Whitehead
  • Patent number: 7372081
    Abstract: A nitride LED having a laminated structure in which a substrate, a n-type cladding layer, an active layer, a p-type cladding layer, and a multi-ohmic contact layer are sequentially stacked, and a manufacturing method thereof, are provided. In the nitride LED, the multi-ohmic contact layer includes multiple layers of a first transparent film layer/silver/second transparent film layer. In the nitride LED and a manufacturing method thereof, ohmic contact characteristics with respect to the p-type cladding layer are enhanced, thereby exhibiting a good current-voltage characteristic. Also, since the transparent electrodes have a high light transmitting property, the light emitting efficiency of the device is increased.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: May 13, 2008
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: June-o Song, Tae-yeon Seong, Dong-seok Leem
  • Patent number: 7291554
    Abstract: A method for forming a semiconductor device includes the steps of forming a flowable film made of an insulating material with flowability; forming a first concave portion in the flowable film through transfer of a convex portion of a pressing face of a pressing member by pressing the pressing member against the flowable film; forming a solidified film having the first concave portion by solidifying the flowable film through annealing at a first temperature with the pressing member pressed against the flowable film; forming a burnt film having the first concave portion by burning the solidified film through annealing at a second temperature higher than the first temperature; forming a second concave portion connected at least to the first concave portion in the burnt film by forming, on the burnt film, a mask having an opening for forming the second concave portion and etching the burnt film by using the mask; and forming a plug and a metal interconnect by filing the first concave portion and the second concav
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: November 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Nakagawa, Masaru Sasago, Yoshihiko Hirai
  • Patent number: 7115497
    Abstract: A method for forming a storage node contact plug of a dynamic random access memory includes forming insulating layers on an overall surface of a semiconductor substrate having a plurality of buried contact plugs, etching the insulating layers down to a top surface of the buried contact plugs to form first contact holes on the buried contact plugs, forming a photoresist pattern on the insulating layers and the first contact holes, etching the insulating layers to form second contact holes on the second insulating layer, and filling the first and second contact holes with conductive material.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 3, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Soon-Kyou Jang
  • Patent number: 6218710
    Abstract: A MOSFET device fabricated by a method that reduces, the risk of gate to source and drain bridging, has been developed. The process features fabricating a polysilicon structure, which is wider at the top than at the bottom, with a source and drain region, self-aligned to the narrower, underlying polysilicon layer. Subsequent metallization results in metal coverage, only on the surfaces of the wider polysilicon layer. An anneal cycle then converts only the wider polysilicon feature to a metal silicide, resulting in a polycide gate structure, comprised of a wider, overhanging metal silicide layer, on a narrower, underlying polysiliocn layer.
    Type: Grant
    Filed: October 1, 1996
    Date of Patent: April 17, 2001
    Assignee: Industrial Technology Research Institute
    Inventor: Chao-Ming Koh
  • Patent number: 6013954
    Abstract: A semiconductor wafer having an SOI (Silicon-On-Insulator) structure and capable of being accurately aligned without undesirable contrast appearing in an infrared transmission image. The wafer is implemented as a laminate SOI wafer including an SOI layer. An aligning oxide film pattern and an oxide film pattern are buried in the SOI layer. The aligning oxide film pattern and oxide film pattern are respectively aligned with an aligning mask pattern and a mask pattern provided on a masking quartz wafer. In this condition, the laminate wafer is subjected to preselected processing. One of opposite major surfaces of the SOI wafer facing the quartz wafer is smoothed over its regions containing at least the aligning oxide film pattern and through which infrared rays are to be transmitted with respect to photoresist. The other major surface is smoothed over the above regions by having a polycrystal silicon film thereof removed.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: January 11, 2000
    Assignee: NEC Corporation
    Inventor: Tomohiro Hamajima
  • Patent number: 5998832
    Abstract: An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the source and drain regions, where the pre-gate regions extend at least partially under the gate electrode. A single heavily doped pre-gate region may be provided for the MOSFET of the electro-static discharge protection circuit.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: December 7, 1999
    Assignee: United Microelectronics, Corp.
    Inventors: Shing-Ren Sheu, Chung-Yuan Lee
  • Patent number: 5969419
    Abstract: By treating the silicon-oxide insulating layer of a semiconductor device with an aqueous metal-salt solution of a metal of an ion radius of less than 0.110 nm, for example, Sc, La or Zr, before a platinum electrode layer is provided on the insulating layer, the platinum layer shows excellent adhesive properties.
    Type: Grant
    Filed: September 8, 1994
    Date of Patent: October 19, 1999
    Assignee: U.S. Philips Corporation
    Inventors: Rudolf P. Tijburg, Karel M. Van Der Waarde
  • Patent number: 5898209
    Abstract: A semiconductor photosensitive element comprises first and second photosensitive regions. The first photosensitive region is different from the second photosensitive region in its structure and thereby the first photosensitive region has photoelectric conversion characteristic and frequency characteristic which are different from those of the second photosensitive region.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: April 27, 1999
    Assignee: Sony Corporation
    Inventor: Shinji Takakura
  • Patent number: 5894156
    Abstract: A resurf structure is provided which includes an n type diffusion region surrounded by a n- diffusion region, in which a part of the joined combination of the n type diffusion region and the n- diffusion region is separated by a narrow p- substrate region in between. An aluminum lead is provided between the separated n- diffusion regions, and a signal is level shifted. A high voltage semiconductor device which includes a small area high voltage isolation region is obtained without process cost increase.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: April 13, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohide Terashima, Kazuhiro Shimizu
  • Patent number: 5883435
    Abstract: The preferred embodiment of the present invention provides a structure and method for personalizing a semiconductor device in the context of a bump array connection to packaging, substrates and such. The preferred embodiment method uses a plurality of conduction lines on said semiconductor device, including a plurality of landing lines and personalization lines. Vias are opened to the plurality of landing lines and selectively opened to a portion of the personalization lines. Connections are made between the opened personalization lines with bumps deposited as part of the bump array.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: March 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Robert Michael Geffken, William Thomas Motsiff, Ronald R. Uttecht
  • Patent number: 5877538
    Abstract: A trench power MOSFET includes a body region which is not shorted to the source region and which is entirely covered by the source region within each cell of the MOSFET. The body region within each MOSFET cell is brought to the surface of the substrate (or epitaxial layer overlying the substrate) in an area outside of the MOSFET cell, and is connected to a body contact bus which is electrically insulated from the source bus. A deep diffusion of the same conductivity type as the body region may be formed adjacent the trench gate but outside of a MOSFET cell to protect the gate oxide from excessive field potentials at the corners of the gate. The deep diffusion is also connected to the body contact bus, which may include a metal layer, a submerged region of the second conductivity, or both.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 2, 1999
    Assignee: Silixonix incorporated
    Inventor: Richard K. Williams
  • Patent number: 5872368
    Abstract: The order parameter of a superconductor is reduced by injecting spin-polarized carriers into the superconductor. The reduction in the order parameter is used to modulate the critical current of the superconductor. In a typical embodiment, a current is caused to flow through a superconductor. Spin polarized electrons are then injected into the path of the current in the superconductor by biasing a magnetic metal with respect to a terminal of the superconductor. The bias current may be varied to modulate the injection and thus the flow of current through the superconductor.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: February 16, 1999
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael Osofsky, Robert J. Soulen, Jr., Raymond Auyeung, James S. Horwitz, Doug B. Chrisey, Mark Johnson
  • Patent number: 5869893
    Abstract: A semiconductor device comprises at least two semiconductor elements connected together at a connecting region of the semiconductor elements. At least one joint chip is adhered to the connection region of the semiconductor elements for connecting the semiconductor elements together. The joint chip has a trapezoidal cross-section defining a first surface and a second surface wider than the first surface. The second surface of the joint chip is adhered to the connection region of the semiconductor elements.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 9, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Osamu Koseki, Takichi Ishii, Masaaki Mandai, Tomoyuki Yoshino, Hitoshi Takeuchi
  • Patent number: 5869866
    Abstract: An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, at least one MDD area, and a heavy concentration source/drain area. Conversely, the PMOS transistor includes an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account, inter alia, the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provides lower source-drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.
    Type: Grant
    Filed: December 6, 1996
    Date of Patent: February 9, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: H. Jim Fulford, Jr., Mark I. Gardner, Derick J. Wristers
  • Patent number: 5869903
    Abstract: A semiconductor device includes a circuit substrate having a first surface on which a high-frequency circuit is located; a first metal layer disposed on a second surface of the circuit substrate; bump wirings on the first surface of the circuit substrate and electrically connected to the high-frequency circuit; a metal wall disposed on the first surface of the circuit substrate surrounding the high-frequency circuit; a wiring substrate having one surface on which substrate wirings corresponding to the bump wirings are located, the wiring substrate being disposed on the circuit substrate so that the substrate wirings are electrically connected to the bump wirings, and in contact with the metal wall, sealing a region including the high-frequency circuit; and a second metal layer disposed on a second surface of the wiring substrate. An electromagnetic shielding effect sufficient for use in a high-frequency circuit is obtained and fabricating cost is considerably reduced.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: February 9, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Mitsunori Nakatani, Hirofumi Nakano
  • Patent number: 5869890
    Abstract: A Ceramic Bonding Copper (CBC) substrate used in semiconductor modules includes a ceramic plate having foil-shaped copper plates bonded to the ceramic plate by the direct copper bonding method. A circuit pattern is formed on one of the copper plates. The ceramic plate is fabricated by sintering at high temperature an alumina powder compact containing zirconia and one or more of the following additives: yttria, calcia, magnesia, and ceria. The flexural strength and the thermal conductivity of the alumnina ceramic plate of the invention are remarkably improved, facilitating a reduction in the thickness of the ceramic plate. The reduction in thickness of the CBC substrate further improves the ability of the semiconductor device to radiate heat and therefore increases the current carrying capability of the semiconductor device.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: February 9, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaharu Nishiura, Akira Morozumi, Tomio Shimizu, Katsumi Yamada, Shigemasa Saito
  • Patent number: 5866936
    Abstract: A mesa-structure avalanche photodiode in which a buffer region in the surface of the mesa structure effectively eliminates the sharply-angled, heavily doped part of the cap layer that existed adjacent the lightly-doped n-type multiplication layer and p-type guard ring before the buffer region was formed. This reduces electric field strength at the ends of the planar epitaxial P-N junction and prevents edge breakdown in this junction. The lateral extent of the guard ring is defined by a window formed in a masking layer prior to regrowth of the guard ring. This guard ring structure eliminates the need to perform additional processing steps to define the lateral extent of the guard ring and passivate the periphery of the guard ring.
    Type: Grant
    Filed: April 1, 1997
    Date of Patent: February 2, 1999
    Assignee: Hewlett-Packard Company
    Inventors: Ghulam Hasnain, James N. Hollenhorst, Chung-Yi Su
  • Patent number: 5866951
    Abstract: The composite hybrid semiconductor structure contains a support plate substrate (11) with a number of at least two support connector spots (13) and a semiconductor chip or semiconductor wafer substrate (10) with a number of at least two chip connector spots (16). The structures is distinguished by a respectively thermally and electrically conducting adhesive layer (13') on the surface of the support plate substrate (11) within the areas of the support connector spots (13), where the said substrates (10, 11) with the said connector spots (13, 16) placed opposite each other and in electrically conducting and mechanically firm connection have been brought into connection with each other by the said electrically conductive adhesive layers (13').
    Type: Grant
    Filed: April 12, 1993
    Date of Patent: February 2, 1999
    Assignee: Robert Bosch GmbH
    Inventors: Lothar Gademann, Peter Flohrs, Juergen Hartmann
  • Patent number: 5861668
    Abstract: A semiconductor package of the present invention includes a paddle layer having a metal wiring pattern formed therein, semiconductor chips bonded on at least one surface of the paddle layer. A plurality of wires electrically connecting a plurality of chip pads formed on the semiconductor chips with the paddle layer. Each lead includes a first lead bonded to a surface of the paddle layer and a second lead which is at least partially exposed. A conductive adhesive bonds the paddle layer to the first leads and a molding resin comprises the body of the package. The semiconductor package of the above construction has various advantages compared to conventional packages. The occupying area rate can be minimized, and an undesired curving of the lead can be prevented. Further, since the semiconductor chip can be bonded on both surfaces of the paddle layer, an integrated semiconductor package can be achieved.
    Type: Grant
    Filed: January 17, 1997
    Date of Patent: January 19, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Gi Bon Cha
  • Patent number: 5859458
    Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.
    Type: Grant
    Filed: July 16, 1996
    Date of Patent: January 12, 1999
    Assignee: Integrated Device Technology, Inc.
    Inventors: Cheng-Chen Calvin Hsueh, Shih-Ked Lee