Abstract: In a lead frame adapted to be used for a semiconductor device, a plurality of inner leads are made of a thin conductive material for easily forming a fine pattern of the inner leads. A plurality of outer leads are integrally formed with the respective inner leads. The outer leads are coated with metal layers to increase the thickness thereof, so that a desired strength of the outer leads is obtained. A semiconductor chip is electrically connected to the inner leads. The semiconductor chip and a part of the lead frame including the inner leads are hermetically sealed with a resin and, thus, a semiconductor device is obtained.

Abstract: A semiconductor device having a controlled resistance value within a predetermined range. The semiconductor device includes a substrate and an oxide layer provided above the substrate. There is also included a first dielectric layer that is silicon-rich above the oxide layer. There is further included a second dielectric layer above the silicon-rich layer.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

Abstract: An apparatus is disclosed for providing a reduced-capacitance transistor with ESD protection that can be fabricated using standard processes. The transistor includes a substrate, a source region formed in the substrate, and a well region also formed in the substrate. The transistor further includes a drain region having a first end region, a second end region, and a resistive region positioned between the first and second end regions. The drain region is formed at least partially in the well region. A drain contract is form on the first end region of the drain region. Additionally, a gate structure is included. The gate structure is formed on the substrate between the source region and the second end region of the drain region. The gate structure defines a channel region that couples the source to the drain region.

Abstract: Between an external power supply line and an internal power supply line in which an internal power supply potential is transmitted on a substrate region, a high voltage conducting mechanism is provided, which is rendered conductive when a transitional high voltage surge is generated at the external power supply line by electrically connecting the external power supply line and the internal power supply line. Even when the ground line and external power supply line are not arranged parallel to each other, a high voltage conducting mechanism constituted by a field transistor or an insulated gate type field effect transistor having wide width over a long distance can be formed.

Abstract: A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion thereof with an electron discharge section, which is formed of metal or semiconductor into a monocrystalline structure or a polycrystalline structure preferentially oriented in at least a direction perpendicular to the substrate by deposition.

Abstract: A semiconductor contact structure formed by a method that deposits an aluminum film limiting the growth of voids and notches in the aluminum film and forms an aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition.

Abstract: A lead frame having a die pad of such a shape that prevents scattering of solder to lead when a chip is mounted on the lead frame, and a semiconductor device using such a lead frame are provided. The lead frame includes a die pad having a region surrounded by a first side, a second side opposing to the first side, a third side different from the first and second sides, and a fourth side opposing to the third side, and a lead formed of a conductor and electrically connected to a semiconductor element. The die pad includes a notch extending along the first and the second sides and positioned opposing to a main surface of the semiconductor element, and a through hole extending along the third and fourth sides and positioned opposing to the main surface of the semiconductor element. The semiconductor device employs the die pad.

Abstract: A method for manufacturing an electronic component by seal-molding with resin a die pad mounted by an electronic element thereon and loads of input-and-output terminals which are supported by a lead frame having an outer frame and removing such sealed electronic component with mold materials from the outer frame of the lead frame which includes suspending pins for supporting the leads and a first mold holder disconnected from the leads, the method including the steps of resin molding a first mold member on the leads and the first mold holder to join the leads and the first mold member with the first mold member, cutting the suspending pins between the first mold member and the outer frame, resin-molding a second mold member on the first mold member to cover the cut ends of the suspending pins, and cutting the first mold holder between the second mold member and the outer frame to remove thus molded electronic component from the lead frame.

Abstract: An integrated circuit comprises a plurality of interconnected semiconductor devices, at least one the interconnected devices being dielectrically isolated from the substrate, and at least one other of the interconnected devices being junction isolated from the substrate. In a preferred embodiment, at least one of the junction isolated devices comprises an ESD protection circuit. The ESD protection circuit, which preferably includes a zener diode and more preferably further includes a bipolar transistor, a diode, and a resistor, is formed in a trench-isolated island comprising a semiconductor layer of a conductivity type opposite to that of the substrate. A heavily doped buried semiconductor region of the same conductivity type as the substrate is formed in the island semiconductor layer adjacent to the substrate.

Abstract: 4-terminal HEMT-HBT composite devices, based upon monolithically integrated HEMT-HBT technology and configured in various topologies, are useful in a wide range of applications which currently utilize discrete MMICs. In particular, the 4-terminal topologies are easily configured as 3-terminal composite devices useful in various 2-port and 3-port MMIC circuit applications, such as low noise-high linearity amplifiers as well as mixers, which provide the benefits of a reduction in size, as well as corresponding cost while providing better performance than utilizing either HEMT or HBT devices individually.

Abstract: In order to provide a thermal coupling between a heat source and a heat sink, an integrated interleaved-fin connector is provided. A first substrate includes a first side surface and a second side surface. A plurality of heat generating devices are formed in the first side surface. A plurality of first channels are etched in the second side surface to form a plurality of first fins. A second substrate has a plurality of second channels etched therein to form a plurality of second fins and a base. The base is for thermally engaging with a heat sink. The first and second fins providing a thermally conductive path from the heat generating devices to the heat sink when interleaved with each other.

Abstract: A heterojunction bipolar transistor in an integrated circuit has intrinsic and extrinsic base portions. The intrinsic base portion substantially comprises epitaxial silicon-germanium alloy. The extrinsic base portion substantially comprises polycrystalline material, and contains a distribution of ion-implanted impurities. An emitter overlies the intrinsic base portion, and a spacer at least partially overlies the emitter. The spacer overhangs the extrinsic base portion by at least a distance characteristic of lateral straggle of the ion-implanted impurities.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A raised-bitline, contactless flash memory device with trenches on a semiconductor substrate doped with a first conductivity type includes a first well of an opposite conductivity type comprising a deep conductor line to a device, and a second well of the first conductivity type above the first well comprising a body line to the device. Deep trenches extend through the second well into the first well. The trenches are filled with a first dielectric. There are gate electrode stacks for a flash memory device including a gate oxide layer over the device. First doped polysilicon floating gates are formed over the gate oxide layer. An interpolysilicon dielectric layer is formed over floating gate electrodes, and control gate electrodes formed of doped polysilicon layer overlie the interpolysilicon dielectric layer. A dielectric cap overlies the control gate electrodes.

Abstract: An electronic device package is provided, consisting of reaction bonded silicon nitride structural and dielectric components and conductor, resistor, and capacitor elements positioned with the package structural components. The package consists of a ceramic package base characterized by a dielectric constant less than 6, of reaction bonded silicon nitride, or a heat spreader material. An electrical conductor is positioned on, embedded in, or attached to the package base for making electrical contact to an electronic device supported on the base and in preferred embodiments, a resistor is attached to the package base. The invention also provides package sidewalls connected to the package base, preferably of reaction bonded silicon nitride, and at least one electrical conductor extending to an outside surface of the package sidewalls for making electrical contact to an electronic device supported by the package base.

Abstract: A semiconductor device including a plurality of chip units each defined by a side wall and arranged in a state such that a side wall of a chip unit abuts a corresponding side wall of an adjacent chip unit, and an interconnection structure for interconnecting a plurality of terminals of a side wall of a chip unit to corresponding terminals of a side wall of an adjacent chip unit that abuts the chip unit at the respective side walls.

Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.