Abstract: An integrated capacitor structure having substantially reduced temperature and voltage coefficients including a combination of conventional N-depletion and P-depletion MOS gate capacitors connected in parallel and optimized for use at low bias voltages, where both the N-depletion and P-depletion capacitor structures have substantially zero temperature coefficients in their fully depleted region of operation.

Abstract: A ferroelectric capacitor includes a substrate and a capacitor electrode on the substrate. A ferroelectric layer is provided on the first capacitor electrode, and a first insulating layer on the ferroelectric layer has a first contact hole therein exposing a portion of the ferroelectric layer. A second capacitor electrode on the first insulating layer makes contact with the ferroelectric layer through the first contact hole. In addition, the second capacitor electrode includes an extension that extends across the first insulating layer away from the first contact hole. A second insulating layer on the second capacitor electrode opposite the substrate has a second contact hole therein exposing a portion of the second insulating capacitor electrode extension opposite the first insulating layer. A conductive line on the second insulating layer makes contact with the exposed portion of a second capacitor electrode extension opposite the insulating layer through the second contact hole.

Abstract: A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.

Abstract: An active matrix device has switching transistors arranged into a matrix pattern on a semiconductor substrate of a first conductivity type. Data is supplied, via signal lines, to sources of the transistors. Turn-on and -off operation of the of the transistors are controlled via gate lines. Pixel electrodes are connected to drains of the transistors. The active matrix device also has semiconductor regions of a second conductivity type opposite to the first conductivity type. The semiconductor regions are formed on the semiconductor substrate so that the semiconductor regions are separated from each other by portions of the semiconductor substrate. The transistors are formed in the semiconductor regions. The semiconductor substrate and the semiconductor regions are reverse-biased with respect to each other.

Abstract: In construction of a plastic molded semiconductor package incorporating a metallic heat sink, the heat sink is made of a thin plate but provided with a central die support depressed from the plane of a surrounding lead support, the section opposite the die support being exposed outside a plastic package. Use of a thin plate as the material enables efficient, continuous processing in production. Presence of the depressed die support assures elongated boundary between the heat sink and the plastic package, thereby effectively reducing undesirable invasion of outer contaminant.

Abstract: The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide by the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a Ge field effect transistor by forming an oxide layer on Ge and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the germanium field effect transistor.

Abstract: An electrically alterable semiconductor memory device having an array of memory cells formed by individual transistors. The structure of the memory cells is compact and facilitates high density memory devices and is particularly well suited for contactless, virtual ground arrays. The memory cells can be read and programmed a page at a time. The memory cells can also be programmed using source-side hot-electron injection with improved efficiency and lowered programming currents.

Abstract: A nonvolatile memory device includes a semiconductor substrate of a first conductivity type; a gate insulating film formed on the substrate; a floating gate having a first region and a second region, the first region lying flat over the gate insulating film and the second region being extended from a first end portion of the first region and perpendicular to the first region; a control gate extending parallel to the second region of the floating gate, lying over the second end portion of the first region of the floating gate and perpendicular to the first region; an inter-insulating layer disposed between the floating gate and the control gate; a first spacer formed at a side wall of the second region of the floating gate and a second spacer formed at a side wall defined by the floating gate and the control gate; a high density source region of a second conductivity type formed in the substrate, being disposed a thickness of the first spacer distant from the floating gate; a first high density drain region of

Abstract: A method and structure for self-aligned zero-margin contacts to active and poly-1, using silicon nitride (or another dielectric material with low reflectivity and etch selectivity to oxide) for an etch stop layer and also for sidewall spacers on the gate.

Abstract: A multi-layered structure is fabricated in which a microprocessor is configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure. Each circuit layer can be fabricated in a separate wafer or thin film material and then transferred onto the layered structure and interconnected.

Abstract: An monolithic integrated circuit comprising a transistor-inductor structure is provided having simultaneously noise matched and input impedance matched characteristics at a desired frequency. The transistor-inductor structure comprises a first transistor Q.sub.1 which may be a common emitter bipolar transistor or common source MOSFET transistor Q.sub.1, a second optional transistor Q.sub.2, a first inductor L.sub.E in the emitter (source) of Q.sub.1, and a second inductor L.sub.B in the base (gate) of Q1. The emitter length l.sub.E1, or correspondingly the gate width w.sub.g, of Q1 is designed such that the real part of its optimum noise impedance is equal to the characteristic impedance of the system, Z.sub.0, which is typically 50.OMEGA.. The first inductor L.sub.E, provides matching of the real part of the input impedance and the second inductor L.sub.B cancels out the noise reactance and input impedance reactance of the structure.

Abstract: The heights of intermediate terminal boards are adjusted to compensate for differences in heights of semiconductor elements on a bottom terminal board. The adjustment places the tops of all intermediate terminal boards in a common plane. A top terminal board applies equal force to all intermediate terminal board to provide uniform mechanical, electrical and thermal connection between the semiconductor devices and both the bottom and top terminal boards.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least one pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to an I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The protection device also includes a second NMOS transistor, merged into the same active area as the first transistor, having a gate region and source region coupled to the ground plane of the mixed voltage integrated circuit. The drain region of the second transistor and the source region of the first transistor is constructed by a shared NMOS diffusion region. This shared diffusion region also constructs the common node coupling the source region of the first transistor to the drain region of the second.

Abstract: A semiconductor device with an LDD structure type MOS transistor is fabricated by forming a gate electrode on a semiconductor layer of a first conductivity type and a source/drain region in the semiconductor layer, the source/drain region having a high impurity concentration region and a low impurity concentration region of a second conductivity type. A pocket of the first conductivity type is formed in contact with the low impurity concentration region only on a drain region side and immediately under the low concentration region of the second conductivity type. The pocket formed only on the drain side can suppress the short channel effect and also the hot carrier generation without lowering the current capacity on the source side where no pocket is present.

Abstract: A bipolar transistor constant voltage source circuit includes a first transistor having a collector connected through a first resistor to VCC, an emitter connected through a second resistor to ground, and a base connected to receive a reference voltage. The collector of the first transistor is connected to a base of a second transistor having a collector connected to VCC and an emitter connected to the ground through third and fourth resistors connected in series. A connection node between the third and fourth resistors is connected to a base of a third transistor having a collector connected through a fifth resistor to VCC and an emitter connected through a sixth resistor to the ground.

Abstract: A metal-semiconductor-metal (MSM) photodetector, specifically a new, improved low noise device is disclosed. The disclosed device is a MSM photodiode in which the cathode and anode are made of different materials with optimal Schottky barrier heights. One of these materials is chosen to provide a high ratio of Schottky barrier height to hole transport and the other to provide a high ratio of Schottky barrier height to electron transport. The disclosed MSM photodetector is designed to allow each Schottky barrier to be individually optimized to the point that a wide bandgap Schottky barrier enhancement layer and its associated heterointerface may become unnecessary. Elimination of the charge buildup at the heterointerface enhances carrier extraction resulting in photodetectors with elevated quantum efficiency and enhanced bandwidths.

Abstract: To obtain an extremely small constant current with high accuracy, a constant current circuit comprises a first constant-current source for producing a first constant current, a second constant-current source connected to the first constant-current source for producing a second constant current having a different value from that of the first current, and an output terminal from which a third constant current equal to the difference between the first and second constant currents is output, such that the third constant current having an extremely small value may be produced without the use of a constant current source capable of producing an extremely small constant current value. The first and second constant current sources may be connected in series with the output terminal connected therebetween, or in parallel through a current mirror circuit. In addition, the constant current circuit can be provided in a timer circuit to produce a very long constant time signal with great stability.

Abstract: An improved metal-semiconductor-metal (MSM) photodiode, specifically a new high responsivity AND high bandwidth photodetector, resulting in a high gain-bandwidth product is disclosed. The disclosed device is an MSM photodiode in which the anode and cathode are made of different materials of differing opacity and possibly including different electrode dimensions as well. Using an opaque anode and a transparent cathode reduces surface reflections off the opaque electrodes allowing more light to be absorbed within the active semiconductor region. However, it concurrently keeps the transit distance for the slower moving holes to a minimum. Thus, the long tail in the impulse response due to hole collection is minimized, resulting in increased bandwidth.

Abstract: A diamond film biosensor has a transducer that is partially or totally composed of semiconducting diamond film and/or undoped diamond film. A bioidentifier is fixed partly or entirely on the surface of said semiconducting diamond film and/or undoped diamond film. The peripheral circuits are partly or entirely composed of undoped diamond film and/or semiconducting diamond film. The diamond film biosensor can detect chemical substances and biosubstances with a high sensitivity and fast response, has a long lifetime, and is reusable.

Abstract: A lead frame having protection against electrostatic discharge is disclosed. The lead frame having protection against electrostatic discharge includes a multiplicity of leads and an electrostatic discharge protection device. The electrostatic discharge protection device includes a conductive layer and a protection layer. The protection layer is arranged to contact a plurality of leads and is formed from an electrostatic discharge protection material, which insulates the leads from the conductive layer at voltages below a predefined threshold voltage and establishes an electrical connection between the leads and the conductive layer at voltages above the threshold voltage.