Patents Examined by Carl Whitehead, Jr.
  • Patent number: 8932937
    Abstract: Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chu-Sheng Lee, Hsin-Chi Chen, Chu-Wei Hu
  • Patent number: 7514358
    Abstract: Embodiments of the invention provide a method for forming tantalum nitride materials on a substrate by employing an atomic layer deposition (ALD) process. The method includes heating a tantalum precursor within an ampoule to a predetermined temperature to form a tantalum precursor gas and sequentially exposing a substrate to the tantalum precursor gas and a nitrogen precursor to form a tantalum nitride material. Thereafter, a nucleation layer and a bulk layer may be deposited on the substrate. In one example, a radical nitrogen compound may be formed from the nitrogen precursor during a plasma-enhanced ALD process. A nitrogen precursor may include nitrogen or ammonia. In another example, a metal-organic tantalum precursor may be used during the deposition process.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: April 7, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Wei Cao, Hua Chung, Vincent Ku, Ling Chen
  • Patent number: 7510966
    Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: March 31, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Qi Pan, Jiutao Li, Yongjun Jeff Hu, Allen McTeer
  • Patent number: 7491642
    Abstract: Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease surface recombination velocities, increase electronic efficiencies, or the like. In other embodiments, the organic passivating layer may be used as a protective sacrificial layer and reduce contact resistance or reduce resistance of doped regions. The organic passivation layer may be formed without the need for high-temperature processing.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: February 17, 2009
    Assignee: The California Institute of Technology
    Inventors: Nathan S. Lewis, William Royea
  • Patent number: 7488634
    Abstract: A method for fabricating a flash memory device is disclosed that improves hot carrier injection efficiency by forming a gate after forming source and drain implants using a sacrificial insulating layer pattern, which includes forming a sacrificial insulating pattern layer over a flash memory channel region of a semiconductor substrate; forming source and drain regions in the semiconductor substrate by ion implantation using the sacrificial insulating pattern layer as a mask; removing portions of the sacrificial insulating pattern layer; sequentially forming an ONO-type dielectric layer and a gate material layer; selectively etching the gate material layer and at least part of the gate dielectric layer to form a gate; and forming gate sidewall spacers at sides of the gate.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: February 10, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Eun Jong Shin
  • Patent number: 7482243
    Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Diane C. Boyd, Bruce B. Doris, Meikei Ieong, Devendra K. Sadana
  • Patent number: 7476967
    Abstract: Embodiments of a composite carbon nanotube structure comprising a number of carbon nanotubes disposed in a matrix comprised of a metal or a metal oxide. The composite carbon nanotube structures may be used as a thermal interface device in a packaged integrated circuit device.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 13, 2009
    Assignee: Intel Corporation
    Inventor: Valery M. Dubin
  • Patent number: 7473995
    Abstract: An integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and a method of making an electronic assembly.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Christopher L. Rumer, Sabina J. Houle, Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Patent number: 7470575
    Abstract: A process for fabricating a semiconductor device including the steps of: introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: December 30, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Takeshi Fukunaga, Akiharu Miyanaga
  • Patent number: 7470593
    Abstract: Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: December 30, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kyoung Bong Rouh, Seung Woo Jin, Min Young Lee
  • Patent number: 7470943
    Abstract: The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 30, 2008
    Assignee: International Business Machines Corporation
    Inventor: Haining S. Yang
  • Patent number: 7468290
    Abstract: Low dielectric materials and films comprising same have been identified for improved performance when used as interlevel dielectrics in integrated circuits as well as methods for making same. In one aspect of the present invention, an organosilicate glass film is exposed to an ultraviolet light source wherein the film after exposure has an at least 10% or greater improvement in its mechanical properties (i.e., material hardness and elastic modulus) compared to the as-deposited film.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: December 23, 2008
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Aaron Scott Lukas, Mark Leonard O'Neill, Jean Louise Vincent, Raymond Nicholas Vrtis, Mark Daniel Bitner, Eugene Joseph Karwacki, Jr.
  • Patent number: 7468306
    Abstract: A semiconductor substrate is provided comprising a plurality of contact pads arranged on a horizontal surface of the semiconductor substrate. Pillars of a first sacrificial material are formed on the contact pads. A first dielectric layer is deposited thus covering at least said pillars. A first conductive layer is deposited between said pillars covered with the first dielectric layer. The pillars are removed thus providing trenches in the first conductive layer having walls covered with the dielectric layer. A second conductive layer is deposited on the first dielectric layer in the trench. A second dielectric layer is deposited such that at least the second conductive layer in the trench is covered by the second dielectric layer. A third conductive layer is deposited on the second dielectric layer.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: December 23, 2008
    Assignee: Qimonds AG
    Inventors: Andreas Thies, Klaus Muemmler
  • Patent number: 7465614
    Abstract: A semiconductor device and method of fabricating the same are provided. The method includes: depositing a silicon layer containing amorphous silicon on a substrate; partially crystallizing the amorphous silicon by applying an annealing process to the silicon layer under an atmosphere of H2O at a predetermined temperature; forming a polycrystalline silicon layer by applying an laser annealing process to the partially crystallized amorphous silicon layer; forming a gate insulating layer on the polycrystalline silicon layer; and forming a gate electrode on the gate insulating layer, so that a substrate is prevented from being bent due to high temperature crystallization while the amorphous silicon is crystallized through an SPC process, thereby reducing defects of the thin film transistor.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: December 16, 2008
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Ramesh Kakkad
  • Patent number: 7465651
    Abstract: Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Sairam Agraharam, Carlton Hanna, Vasudeva Atluri, Dongming He
  • Patent number: 7462927
    Abstract: A pattern film forming method includes a step of producing a transfer sheet in which a thin film is formed on a surface of a sheet-shaped material and a step of pressing the thin film against a pattern film formation surface of the substrate with a pressing member having convex portions corresponding to the pattern film from a reverse surface of the transfer sheet opposite to the thin film or a reverse surface of the substrate opposite to the pattern film formation surface to transfer the thin film to the substrate. A pattern film forming apparatus includes a sheet supply device, a pressing device and a substrate transport device. A high-definition pattern film having a desired pattern and a sharp edge can be formed with high productivity.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: December 9, 2008
    Assignee: FUJIFILM Corporation
    Inventors: Jun Fujinawa, Junji Nakada, Norio Shibata, Takashi Kataoka
  • Patent number: 7462512
    Abstract: Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.
    Type: Grant
    Filed: January 11, 2005
    Date of Patent: December 9, 2008
    Assignee: Polytechnic University
    Inventors: Kalle Levon, Arifur Rahman, Tsunehiro Sai, Ben Zhao
  • Patent number: 7459392
    Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez, Michael L. McSwiney
  • Patent number: 7456080
    Abstract: Methods and apparatus for producing a semiconductor on glass (SOG) structure include: subjecting an implantation surface of a donor semiconductor wafer to multiple ion implantation processes to create an exfoliation layer in the donor semiconductor wafer, wherein at least one of: (i) the type of ion, (ii) the dose, and/or (iii) the implantation energy of at least two of the multiple ion implantation processes differ from one another.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: November 25, 2008
    Assignee: Corning Incorporated
    Inventor: Kishor Purushottam Gadkaree
  • Patent number: RE41310
    Abstract: A method is disclosed for growing a nitrogen-containing III-V alloy semiconductor on a semiconductor substrate such as GaAs, which is formed by MOCVD method using nitrogen containing organic compounds having relatively low dissociation temperatures. The alloy semiconductor has a high nitrogen content which exceeds the contents previously achieved, and has a high photoluminescence intensity. There are also disclosed fabrications of semiconductor devices comprising the alloy semiconductors, such as heterostructure and homo-junction light emitting devices.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: May 4, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Shunichi Sato