Abstract: A method for controlling a number of phases that are active in a multiphase direct-current-to-direct-current (DC-to-DC) converter includes (a) filtering a current signal representing a magnitude of current processed by the multiphase DC-to-DC converter to generate a filtered signal, (b) comparing the filtered signal to a first threshold value, (c) deactivating one or more phases of the multiphase DC-to-DC converter in response to the filtered signal falling below the first threshold value, (d) comparing the current signal to a second threshold value, the second threshold value being greater than the first threshold value, and (e) activating one or more phases of the multiphase DC-to-DC converter in response to the current signal rising above the second threshold value.

Abstract: A converter arrangement for an AC system includes a phase leg including a first sub-converter, a second sub-converter, an IPT interface configured for connecting the first and second sub-converters with a phase line A, and at least one DC bus connected to the first and second sub-converters. The first sub-converter is connected in parallel with the second sub-converter between the DC bus and the IPT interface. Each of the first and second sub-converters includes a chain-link converter connected to the IPT interface and including a plurality of converter cells connected in series with each other, and a common DC link multilevel converter connected to the DC bus and in series with the chain-link converter.

Abstract: An electric power conversion device which performs conversion to desired voltage using charge and discharge of a DC capacitor includes: a reactor connected to a rectification circuit; a leg part in which diodes and first and second switching elements are connected in series between positive and negative terminals of a smoothing capacitor, and to which the reactor is connected; and the DC capacitor. A control circuit performs high-frequency PWM control for the first and second switching elements using the same drive cycle, with their reference phases shifted from each other by a half cycle, and controls a sum and a ratio of ON periods of the first and second switching elements in one cycle, thereby allowing both high-power-factor control for input AC current and voltage control for the DC capacitor.

Abstract: A control circuit for a switched mode power supply (SMPS) has an input voltage reference voltage generator arranged to receive a signal indicative of an input voltage of the SMPS and is arranged to generate a reference signal directly proportional to the input voltage. An error signal generator of the control circuit is arranged to receive a signal indicative of an output voltage of the SMPS and arranged to generate an error signal based on the reference signal generated by the input reference voltage generator and based on the output voltage of the SMPS. A duty cycle control signal generator of the control circuit is arranged to generate a control signal, to control the duty cycle of the SMPS, in dependence upon the error signal.

Abstract: An inverter includes a first bridge leg, first to fourth MOSFET switches; a second bridge leg, connected in parallel with the first bridge leg, and fifth to eighth MOSFET switches; a third bridge leg, electrically coupled between a first node and a second node, and ninth to twelfth MOSFET switches; a first diode, connected in parallel with the anti-series connected first and second MOSFET switches; a second diode, connected in parallel with the anti-series connected third and fourth MOSFET switches; a third diode, connected in parallel with the anti-series connected fifth and sixth MOSFET switches; a fourth diode, connected in parallel with the anti-series connected seventh and eighth MOSFET switches; a fifth diode, connected in parallel with the anti-series connected ninth and tenth MOSFET switches; a sixth diode, connected in parallel with the anti-series connected eleventh and twelfth MOSFET switches.

Abstract: An active clamp flyback controller includes first and second input terminals, a clamp voltage detection circuit, and an overvoltage protection circuit. The first input terminal is adapted to be coupled to a terminal of a clamp capacitor. The second input terminal receives a feedback signal proportional to a voltage across an auxiliary winding of a flyback transformer. The clamp voltage detection circuit is coupled to the first and second input terminals, and detects a clamp voltage as a difference between a voltage at the first input terminal and an input voltage, the clamp voltage detection circuit calculating the input voltage using a signal from the second input terminal. The overvoltage protection circuit is coupled to the clamp voltage detection circuit for comparing the clamp voltage to a threshold and triggering a protection operation if the clamp voltage is greater than the threshold.

Abstract: A power supply circuit includes a DC-DC converter and a choke coil. The choke coil includes a pair of coils wound in mutually opposite directions, and the coils are connected between a DC power source and the DC-DC converter. In the choke coil, a self-resonating frequency in a common mode is higher than a self-resonating frequency in a normal mode. In the choke coil, a normal mode impedance at the highest frequency in an AM band is higher than a common mode impedance at the lowest frequency in an FM band.

Abstract: A comparator circuit includes a first comparator arranged to compare an input signal with a reference voltage so as to generate a first comparison signal, a second comparator arranged to compare the input signal with a variable reference voltage so as to generate a second comparison signal, a variable reference voltage generator arranged to generate the variable reference voltage, and a logic unit arranged to output one of the first comparison signal and the second comparison signal as a comparison signal. The logic unit outputs the first comparison signal as the comparison signal while controlling the variable reference voltage generator to sweep the variable reference voltage until the first comparison signal and the second comparison signal exhibit desired response behaviors, and moves to a state capable of outputting the second comparison signal as the comparison signal after the sweep of the variable reference voltage is completed.

Abstract: The disclosure discloses a virtual impedance comprehensive control method for an inductive power filtering (IPF) system. According to the disclosure, harmonic damping control at grid side and zero impedance control of filters are organically combined according to a technical problem which is unsolved and process difficulty in equipment manufacturing in an existing filtering method, so that the problem of performance reduction of passive filtering equipment caused by a change in an impedance parameter of a power grid system is solved on one hand, optimization control over a quality factor of the passive filtering equipment may be implemented to reduce dependence on an equipment production process level on the other hand, a quality factor of the single-tuned filters may meet a design requirement, and an overall filtering characteristic is further improved.

Abstract: An embodiment of a buck-boost power converter may include an inductor driver section configured to control four switches to control an output of the converter, and a PWM circuit to generate a PWM control signal responsive to an output level of the output. An embodiment of a switch control is configured to, when an on time of the second switch becomes less than a specified entry value, force the third switch to generate boot refreshing pulses with an on time of a specified duration value at a rate more than a specified frequency, and when an on time of the third switch becomes less than the specified entry value, force the second switch to generate boot refreshing pulses with an on time of the specified duration value at the rate more than the specified frequency.

Abstract: An external circuit element RSET is connected in use to an SET terminal. A synchronous rectification controller generates a pulse signal S1 based on a control time determined according to the state of the SET terminal. A driver switches on and off the synchronous rectification transistor according to the pulse signal S1. An abnormal state detection circuit is capable of detecting an open-circuit state and/or a short-circuit state that can occur in the SET terminal. When the abnormal state detection circuit detects such an open-circuit state and/or short-circuit state, the abnormal state detection circuit asserts a detection signal S11. When the detection signal S11 is asserted, a primary-side controller arranged on the primary side of the DC/DC converter is instructed to suspend the switching operation of a switching transistor.

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.

Abstract: This power conversion device includes a rectification circuit, a reactor, an inverter circuit, and an isolation transformer. The inverter circuit is composed of a first leg A, a second leg B, and a DC capacitor connected in parallel between DC buses. A first AC end of the first leg A is connected to a positive DC terminal of the rectification circuit via the reactor. High power factor control of current iac flowing from an AC power supply via the rectification circuit is performed by PWM control for the first leg A, and voltage Vdc of the DC capacitor is controlled by PWM control for the second leg B using a duty cycle equal to or smaller than that for the first leg A, thereby controlling power outputted to the secondary side of the isolation transformer.

Abstract: An apparatus for producing unvarying direct load current comprises a direct voltage source connected to a DC-to-pulse voltage converter connected through a first galvanic decoupler to a pulse-to-DC voltage converter connected to a first terminal of the load. Another terminal of the load is connected to a DC stabilizer connected to a control circuit which is connected through a second galvanic decoupler to a control input of the DC-to-pulse voltage converter. Disclosed are three versions of the apparatus differing by the way the load is connected. The apparatus provides unvarying direct current flowing through the load that can vary within a wider load range.

Abstract: A switching power converter is provided that extrapolates from a reference voltage during dead periods of a rectified input voltage as determined from a comparison of an Isense voltage to a current threshold.

Abstract: A switching regulator circuit incorporates an offset circuit, connected in a control loop of the regulator circuit, that, in response to a signal indicating an imminent load current step, adjusts a duty cycle of a power switch for the current step prior to the regulator circuit responding to a change in output voltage due to the current step. In one embodiment, a load controller issues a digital signal shortly before a load current step. The digital signal is decoded and converted to an analog offset signal in a feedback control loop of the regulator to immediately adjust a duty cycle of the switch irrespective of the output voltage level. By proper timing of the offset, output voltage ripple is greatly reduced. The current offset may also be used to rapidly change the output voltage in response to an external signal requesting a voltage step.

Abstract: A switching shunt regulator circuit includes a current source having an input for receiving an input voltage and an output for providing a DC current, and a shunt voltage regulator coupled to the output of the current source. The current source is configured to provide DC current to a DC load and DC current to the shunt voltage regulator when the DC load is coupled to the output. The DC current to the shunt voltage regulator regulates a voltage at the output. The shunt voltage regulator has a current carrying capacity greater than the sum of the DC current to the DC load and the DC current to the shunt voltage regulator.

Abstract: A combined voltage regulator and snubber circuit generally has a voltage regulator device in parallel with the energy storage element of the snubber circuit operatively connectable in series with a leakage inductance current path; the leakage inductance being part of a magnetic component utilized in a switch-mode power supply having an input voltage source, controllable semiconductor switches, freewheeling semiconductor switches, feedback controller, reactive energy storage components and a load; the voltage regulator generally providing constant or variable voltage to the gate driver of the controllable semiconductor and/or feedback controller.

Abstract: In a first period having a first period length, first data and second data are alternately given to an inverter control unit. The first data has a first value indicating a length of time from the start point of time of the first period to a matching point of time as a point of time when a converter carrier takes a converter threshold value and an inverter threshold value corresponding to a second period having the first value as its length. The second data has a second value indicating a length of time from the matching point of time to the end point of time of the first period and an inverter threshold value corresponding to a second period having the second value as its length.

Abstract: A method for performing phase shedding for a voltage converter having a multi-phase output stage circuit includes: sensing an input current of the voltage converter to generate a first digital signal when enabling at least one first output stage within the multi-phase output stage circuit; sensing the input current of the voltage converter to generate a second digital signal when further enabling a second output stage within the multi-phase output stage circuit; comparing the first digital signal with the second digital signal to generate a comparison resultant signal; dynamically adjusting the phase shedding threshold according to the comparison resultant signal, to automatically search/determine an optimal phase shedding threshold; and, performing the phase shedding when an operation of the voltage converter exceeds the optimal phase shedding threshold.