Abstract: An example heterostructure semiconductor for sensing a gas comprises a substrate made of nanosheets of a compound of a first metal, wherein the compound of the first metal is sensitive to the gas to be sensed; one or more 1-Dimensional (1D) components fabricated on a surface of the substrate, the 1D components comprising a compound of a second metal, wherein the compound of the second metal is selective to the gas to be sensed; and a 2-Dimensional (2D) layer formed on the surface of the substrate in portions excluding the 1D components, wherein the 2D layer comprises compounds of the first and second metal. Method of fabrication of the heterostructure semiconductor and a chemiresistive sensor made thereof are also disclosed.

Abstract: A display module is disclosed. The display module includes pixels provided on the substrate, one of which includes: inorganic light emitting elements configured to emit light of a same color; light dispersing layers provided on light emitting surfaces of the inorganic light emitting elements; color conversion layers provided on the light dispersing layers; and color filters provided on the color conversion layers. When viewed from above an upper surface of the substrate, the light dispersing layers are larger than the inorganic light emitting elements.

Abstract: The present disclosure discloses a light-emitting substrate, a method for forming the light-emitting substrate and a display device. The light-emitting substrate includes: a base substrate; a first signal line located at one side of the base substrate; an insulation layer located at one side of the first signal line away from the base substrate; an electrode layer located at one side of the insulation layer away from the base substrate and including a first electrode terminal, a second electrode terminal and a second signal line, where the first electrode terminal is electrically connected to the first signal line via a first through hole penetrating the insulation layer; and at least one light-emitting element bound and connected to the first electrode terminal and the second electrode terminal.

Abstract: The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

Abstract: A method for manufacturing an image display device includes: providing a semiconductor growth substrate comprising a semiconductor layer on a first substrate, the semiconductor layer comprising a light-emitting layer; providing a second substrate comprising a circuit, wherein the circuit comprises a circuit element; forming a light-shielding layer on the second substrate; forming an insulating film on the light-shielding layer; bonding the semiconductor layer to the second substrate on which the insulating film is formed; forming a light-emitting element by etching the semiconductor layer; forming an insulating layer that covers the light-emitting element; and electrically connecting the light-emitting element to the circuit element. The light-shielding layer is located between the light-emitting element and the circuit element. In a plan view, the light-shielding layer covers the circuit element.

Abstract: A method for manufacturing semiconductor device structure includes providing a substrate having a surface; forming a first gate structure on the surface; forming a second gate structure on the surface; forming a first well region in the substrate and between the first gate structure and the second gate structure; forming a conductive contact within a trench between the first gate structure and the second gate structure; forming a first structure in the first well region, wherein the first structure tapers away from a bottom portion of the conductive contact.

Abstract: A semiconductor structure includes a base layer, a metal-containing gate, a high-k layer and a spacer. The metal-containing gate is disposed over the base layer. The high-k layer is disposed between the base layer and the metal-containing gate. The high-k layer has a protruding portion that protrudes out from a bottom of the metal-containing gate. The spacer is disposed on the sidewall of the metal-containing gate and covers the protruding portion of the high-k layer.

Abstract: An integrated circuit (IC) device includes a fin-type active region extending in a first lateral direction on a substrate, a gate line extending in a second lateral direction on the fin-type active region, an insulating spacer covering a sidewall of the gate line, a source/drain region at a position adjacent to the gate line, a metal silicide film covering a top surface of the source/drain region, and a source/drain contact apart from the gate line with the insulating spacer therebetween in the first lateral direction. The source/drain contact includes a bottom contact segment being in contact with a top surface of the metal silicide film and an upper contact segment integrally connected to the bottom contact segment. A width of the bottom contact segment is greater than a width of at least a portion of the upper contact segment in the first lateral direction.

Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

Abstract: A ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored depending on whether first and second local interconnects connected to the nodes of the first transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line. Second data is stored depending on whether third and fourth local interconnects connected to the nodes of the second transistor are connected to a same line, or different lines, out of a bit line and a ground power supply line.

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer is arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

Abstract: A display apparatus includes: a lower substrate including a display area and a transmission area; first to third pixel electrodes in the display area; an intermediate layer having an opening corresponding to the transmission area; an opposite electrode above the intermediate layer, and having an opening corresponding to the transmission area; an upper substrate including a first area corresponding to the first pixel electrode, a second area corresponding to the second pixel electrode, a third area corresponding to the third pixel electrode, and a fourth area corresponding to the transmission area; a light-transmissive layer in the first area; a second-color quantum dot layer in the second area; a third-color quantum dot layer in the third area; and a light-transmissive material layer be in the fourth area, and being integrally formed with the light-transmissive layer.

Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface. The first surface includes an element isolation trench. An element isolation layer is arranged inside the element isolation trench. The element isolation layer defines an active region. A gate electrode is arranged on the first surface of the semiconductor substrate. An interlayer insulating layer is arranged on the first surface of the semiconductor substrate and covers the gate electrode. A ground contact is configured to penetrate the element isolation layer and the interlayer insulating layer and contacts the semiconductor substrate. A color filter is arranged on the second surface of the semiconductor substrate.

Abstract: A method includes: forming a sacrificial gate structure on the active region; forming a spacer structure including a first spacer, a second spacer, and an air-gap spacer, the air-gap spacer capped by bending an upper portion of the second spacer toward an upper portion of the first spacer; forming an insulating structure on the sides of the spacer structure; forming a gap region; and forming a gate structure including a gate dielectric layer, a gate electrode, and a gate capping layer in the gap region. The upper portion of the second spacer is in physical contact with the upper portion of the first spacer on a contact surface, and a lowermost end of the contact surface is on a level higher than an upper surface of the gate electrode with the substrate being a reference base level.

Abstract: A display device includes: a display element provided to a display region; an analysis element provided to a frame region disposed around the display region; and a sealing layer sealing the display element and the analysis element. The display element includes: a TFT layer including a resin film; and a light-emitting element layer including a first electrode, a functional layer, and a second electrode. The analysis element includes: a first metal film formed on the resin film; an analysis layer formed on the first metal film; a second metal film formed to cover at least a portion of an edge of the analysis layer, and electrically connected to the first metal film; and a ground wire electrically connected through the first metal film to the second metal film.

Abstract: A sensor includes first and second electrodes, and an infrared photoelectric conversion layer between the first and second electrodes, the infrared photoelectric conversion layer being configured to absorb light in at least a portion of an infrared wavelength spectrum and convert the absorbed light to an electrical signal. The infrared photoelectric conversion layer includes a first material having a maximum absorption wavelength in an infrared wavelength spectrum, a second material forming a pn junction with the first material, and a third material having an energy band gap greater than the energy band gap of the first material by greater than or equal to about 1.0 eV. The first material, the second material, and the third material are different from each other, and each of the first material, the second material, and the third material is a non-polymeric material.

Abstract: For example, a semiconductor device includes a split-gate power transistor configured to have a plurality of channel regions controlled individually according to a plurality of gate control signals, a gate control circuit configured to generate the plurality of gate control signals, and an overcurrent protection circuit configured to turn off at least one of the plurality of channel regions when the output current passing through the power transistor exceeds a threshold voltage.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

Abstract: A memory and a method for manufacturing the same are provided. The memory includes a substrate; at least one pair of transistors on a surface of the substrate, in which conductive channels of the transistors extend in a direction perpendicular to the surface of the substrate; storage layers, which each are located, in the direction perpendicular to the surface of the substrate, on a side surface of each of the transistors, the storage layers are interconnected with the conductive channels of the transistors, any one of the storage layers is located between the pair of transistors, and the storage layers are configured to store electric charges and transfer the electric charges between the storage layers and the conductive channels interconnected therewith.

Abstract: A memory array includes hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source/drain electrode extending on the channel layer; and a second source/drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source/drain electrode and the channel layer.