Patents Examined by Cathy F. Lam
  • Patent number: 7524552
    Abstract: To provide a dielectric-layer-provided copper foil or the like for extremely improving the product yield while making the most use of the increase effect of an electric capacity of a thin dielectric layer using the sputtering vapor deposition method. In the case of dielectric-layer-provided copper foils respectively having a dielectric layer on one side of a copper foil, the dielectric layer 6 is an inorganic-oxide sputter film having a thickness of 1.0 ?m or less and formed on the one side of the copper foil in accordance with the sputtering vapor deposition method and the dielectric-layer-provided copper foils for respectively forming a capacitor layer, characterized in that a pit-like defective portion generated on the inorganic-oxide sputter film is sealed by polyimide resin are used.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 28, 2009
    Assignee: Mitsui Mining and Smelting Co., Ltd.
    Inventors: Toshiko Yokota, Tetsuhiro Matsunaga, Susumu Takahashi, Hideaki Matsushima, Takuya Yamamoto, Makoto Dobashi
  • Patent number: 7459044
    Abstract: A sheet comprising thermoplastic polymer (TP) and short high tensile modulus fibers, in which the concentration of TP in the middle of the sheet is higher than at the surface of the sheet, useful for making prepregs with a thermoset resin.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: December 2, 2008
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Subhotosh Khan, Michael Robert Samuels, Mikhail R. Levit
  • Patent number: 7455915
    Abstract: Application of a conductive material with a compliant underlayer onto selected pads of a substrate, includes forming at least one padstack, by patterning a sheet including a stack of material layers. Padstacks may include a first conductive top layer, one or more underlying layers, and a bottom attachment layer, such as a solder layer. At least one flexible, or compliant, layer is disposed in the sheet between the top and attachment layers. The compliant layer may be a conductive elastomer. The top layer of the padstacks are adhered to a soluble tape, and this composite structure is moved into place over the circuit board by means of a pick and place operation. The placement of the padstacks is followed by a solder reflow to adhere the padstacks to the contact pads of the substrate, and by a wash cycle with a solvent to remove the soluble tape.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: November 25, 2008
    Inventor: Morgan T. Johnson
  • Patent number: 7440256
    Abstract: A laminated ceramic substrate includes a side electrode in which a side edge electrode layer formed on a side edge portion of a ceramic layer overlaps with and connects to a side edge electrode layer formed on a side edge portion of another ceramic layer directly above and/or directly below the former ceramic layer. The side edge electrode layer includes a parallel wall unexposed and approximately parallel to a side surface of the laminated ceramic substrate and a perpendicular wall approximately perpendicular to the side surface of the laminated ceramic substrate. A length La of the parallel wall and a depth Lb of the parallel wall from the side surface of the laminated ceramic substrate have a relationship of La>Lb.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masanori Hongo, Hiroyuki Nishikiori, Natsuyo Nagano, Takashi Ogura
  • Patent number: 7423220
    Abstract: A conductive paste for multilayer electronic components which is to be directly printed on a ceramic green sheet, the conductive paste contains a conductive powder, a resin and an organic solvent, wherein the organic solvent contains at least one solvent selected from an alkylene glycol diacetate and an alkylene glycol dipropionate. A multilayer electronic component is obtained by firing at high temperature an unfired laminate prepared by alternately stacking ceramic green sheets and internal electrode paste layers in which each of the internal electrode paste layers is formed by the above conductive paste. The conductive paste has appropriate viscosity characteristics and long-term stability, which allows manufacturing highly reliable multilayer electronic components having excellent electrical characteristics, without causing sheet attack.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 9, 2008
    Assignee: Shoei Chemical Inc.
    Inventors: Toshio Yoneima, Kaori Higashi
  • Patent number: 7396591
    Abstract: In a wiring substrate having a metal wiring pattern that is formed on a substrate and includes a contact portion for providing connection to an external element, an organic thin film containing silane is formed to cover the metal wiring pattern and the contact portion is electrically connected to the external element through the organic thing film. Unlike conventional wiring substrates in which a contact portion is uncovered by ripping open or cutting away a protective resin film formed on the contact portion, the wiring substrate can be electrically connected with an external element having a low contact pressure, for example.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: July 8, 2008
    Assignee: Japan Aviation Electronics Industry Limited
    Inventors: Takuya Miyashita, Masafumi Okada, Kenji Matsumoto
  • Patent number: 7393580
    Abstract: A layered board is disclosed which can avoid the occurrence of cracks in a core layer due to shearing stress caused by a difference in coefficient of thermal expansion between the core layer and a buildup layer. The layered board includes a core layer which serves as a printed board, a buildup layer which includes an insulation part and a wiring part, is overlaid on the core layer, and is electrically connected to the core layer, and an edge layer formed at least at an edge on the periphery of the core layer, the edge layer being different from the core layer. Alternatively, the core layer projects outward from an edge on the periphery of the buildup layer.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: July 1, 2008
    Assignee: Fujitsu Limited
    Inventor: Takashi Kanda
  • Patent number: 7388296
    Abstract: A wiring substrate comprised of a substrate main body made of glass-ceramic, a pad formed on a surface of the substrate main body and a conductor pin provided in an upright position on the pad. The pad is comprised of a ceramic that is the same as the ceramic constituting the glass-ceramic, Fe converted into Fe2O3 and Cu. The Fe2O3 comprises 1 to 28 parts by weight with respect to 100 parts by weight of the Cu.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 17, 2008
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Kazuhiro Urashima, Tatsuharu Ikawa, Mitsuo Shiraishi, Hiroshi Sumi
  • Patent number: 7384683
    Abstract: The present invention provides a substrate for a flexible printed wiring board including an adhesive layer containing an epoxy resin composition, insulating layers respectively stacked on both sides of the adhesive layer and formed with a pair of films containing a nonthermoplastic polyimide resin, and conductor layers respectively disposed on the outer surfaces of the films. The total thickness of the insulating layers respectively stacked on both sides of the adhesive layer is 10 to 100 ?m and 2 to 10 times the thickness of the adhesive layer. The mutual adhesion strength between the insulating layers through the intermediary of the adhesive layer is 7.0 N/cm or more.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 10, 2008
    Assignees: Unitika Ltd., Nippon Kayaku Kabushiki Kaisha
    Inventors: Yoshiaki Echigo, Jusirou Eguchi, Akira Shigeta, Makoto Uchida, Shigeru Moteki
  • Patent number: 7374811
    Abstract: A method for manufacturing a ceramic device is provided. The ceramic device comprises a ceramic layer. A polyimide layer is on the ceramic layer. The polyimide layer has disposed therein a plurality of copper vias. Each copper via is in physical contact with the ceramic layer. A plurality of pads are formed on the polyimide layer. Each of the plurality of pads is in physical contact with a copper via of the plurality of copper vias. In this way, the pads are supported by a continuous copper arrangement, thereby providing greater support for the probe pads than if the probe pads were supported by the polyimide layer, as the mechanical strength of polyimide layer is lower than the mechanical strength of copper.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: May 20, 2008
    Assignee: SV Probe Pte Ltd.
    Inventors: Chi Shih Chang, Bahadir Tunaboylu
  • Patent number: 7371475
    Abstract: The target for the transparent conductive thin film having indium oxide as its major component and containing tungsten and/or molybdenum, obtained by forming a body of indium oxide powder, and tungsten oxide power and/or molybdenum oxide powder and then heating or sintering the formed body such that the thin film after sputtering has indium oxide as the main component and contains tungsten and/or molybdenum with an atomic ratio (W+Mo)/In of 0.0040 to 0.0470, whereby a transparent conductive thin film having excellent surface smoothness and low specific resistance of 6.0×10?4 ?·cm or less, and whose surface smoothness and specific resistance properties do not change even when heated at 170° C. is provided.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 13, 2008
    Assignee: Sumitomo Metal Mining Co., Ltd.
    Inventor: Yoshiyuki Abe
  • Patent number: 7371471
    Abstract: An electromagnetic noise suppressing thin film has a structure including an inorganic insulating matrix made of oxie, nitride, fluoride, or a mixture thereof and columnar-structured particles made of a pure metal of Fe, Co, or Ni or an alloy containing at least 20 weight % of Fe, Co, or Ni and buried in an inorganic insulating matrix.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: May 13, 2008
    Assignee: NEC TOKIN Corporation
    Inventors: Shigeyoshi Yoshida, Hiroshi Ono, Yutaka Shimada, Tetsuo Itoh
  • Patent number: 7351676
    Abstract: A dielectric ceramic composition of the present invention includes 100 parts by mole of BaTiO3, x1 parts by mole of MnO, x2 parts by mole of Cr2O3, x3 parts by mole of Y2O3 and/or Ho2O3, x4 parts by mole of oxide selected from the group consisting of BaO, CaO and SrO, and x5 parts by mole of SiO2 and/or GeO2, where 0.5?x1?4.5, 0.05?x2?1.0, x1+x2?4.55, 0.25?x3?1.5, 0.5 ?x4?6 and 0.5?x5?6. A multilayer ceramic capacitor of the present invention includes a laminated structure of a ceramic dielectric made of such a composition and an electrode made of Ni or Ni alloy.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: April 1, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Koga, Yukio Tominaga, Tetsuhiro Takahashi
  • Patent number: 7348045
    Abstract: A dielectric film for use as a substrate for a flexible circuit comprises a polymer selected from the group consisting of liquid crystal polymers and polyimide copolymers including carboxylic ester structural units in the polymeric backbone. The dielectric film has a thickness from about 25 ?m to about 60 ?m including at least one thinned, recessed region wherein the thickness is reduced to less than 15 ?m, as required for use of the dielectric film in e.g. ink jet print head, hard disk drive head gimbal assembly and touch sensor applications.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: March 25, 2008
    Assignee: 3M Innovative Properties Company
    Inventors: Rui Yang, Christopher G. Dunn, Nathan P. Kreutter
  • Patent number: 7348069
    Abstract: A first ceramic substrate includes a substrate (2) and a glaze layer (3), wherein the glaze layer has a surface having an Ra of 0.02 ?m or less and a Ry of 0.25 ?m or less. A second ceramic substrate is formed by subjecting a glass layer (24) formed on a surface of a substrate (2) to heating-and-pressurizing treatment, thereby forming a glaze layer (3) on the substrate (2), and planarization-polishing the surface of the glaze layer. A third ceramic substrate includes a substrate (2), a glaze layer (3) containing substantially no pores formed on the substrate (2) and the surface thereof being planarization-polished, and a wiring pattern (21), wherein at least one first end of the wiring pattern is exposed to the glaze layer (3) surface of the substrate (1), and at least one second end is exposed to another surface of the substrate (1).
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: March 25, 2008
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Seiji Ichiyanagi, Jun Otsuka, Manabu Sato, Masahiko Okuyama
  • Patent number: 7344785
    Abstract: A copper foil 1 comprises a roughened plating layer 2, a Ni—Co alloy plating layer 3, a zinc galvanized (underlying) layer 4, a chromate treatment layer 5, and a silane coupling treatment layer 6 on a surface to be bonded with a base material for a printed circuit board, and the chromate treatment layer 5 is formed by using a trivalent chromium conversion treatment solution containing 70 mg/L or more and less than 500 mg/L of trivalent chromium ions converted into metal chromium and having a pH-value of 3.0 to 4.5. According to the present invention, a copper foil for a printed circuit board, a method for fabricating the same, and a trivalent chromium conversion treatment solution used for fabricating the same, which have an excellent controllability in Zn film forming amount and chromate film forming amount can be obtained.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: March 18, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Muneo Kodaira, Shingo Watanabe, Gen Sasaki, Yasuyuki Ito, Katsumi Nomura
  • Patent number: 7338716
    Abstract: This invention relates to a laminate comprising an insulating polyimide resin layer etchable by an aqueous alkaline solution and a metal foil. The laminate has an insulating resin layer composed of a plurality of polyimide resin layers on the metal foil and the insulating resin layer has at least one polyimide resin layer (A) with a coefficient of linear thermal expansion (CTE) of 30×10?6/° C. or less and at least one polyimide resin layer (B) with a glass transition temperature (Tg) of 300° C. or below, the layer in contact with the metal foil is the polyimide resin layer (B), the bonding strength between the metal foil and the polyimide resin layer (B) in contact therewith is 0.5 kN/m or more, and the average rate of etching of the insulating resin layer by a 50 wt % aqueous solution of potassium hydroxide at 80° C. is 0.5 ?m/min or more. The laminate is useful for flexible printed circuits and the like.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: March 4, 2008
    Assignee: Nippon Steel Chemical Co., Ltd.
    Inventors: Kazuto Okamura, Kazutoshi Taguchi, Kazunori Ohmizo, Makoto Shimose
  • Patent number: 7335414
    Abstract: A printed circuit board has a flexible portion where a covering layer is exposed, and a rigid portion provided by forming a resistant layer on a part of the covering layer. To produce a camera module, a lens unit and a CCD are affixed to the printed circuit board through an adhesive, wherein the CCD is located inside the lens unit. The rigid portion has a top surface that is substantially equal in shape and size to an outline of a bottom surface of the lens unit, so the top surface of the rigid portion serves as a coating area for the adhesive.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: February 26, 2008
    Assignee: FUJIFILM Corporation
    Inventor: Setsu Takeuchi
  • Patent number: 7332212
    Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: February 19, 2008
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
  • Patent number: RE40436
    Abstract: An electronic display screen is created by processing a mirror on a substrate glass. A back plate glass is then placed on top of the substrate glass and sealed to the back plate glass. A hermetic seal that includes an adhesive mixed with zeolites is disclosed. The hermetic seal can seal the back plate glass with the substrate glass. The application of the hermetic seal is not limited to the electronic display screen. Rather, the hermetic seal can be used to seal a variety of surfaces including metals, polymers, plastics, alloys, ceramics and the like.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: July 15, 2008
    Assignee: IDC, LLC
    Inventors: Manish Kothari, Clarence Chui