Patents Examined by Cathy F. Lam
  • Patent number: 7239027
    Abstract: A bonding structure of device packaging includes a first substrate and a second substrate. The surfaces of the first substrate have metal pads and a first bonding layer connected to the second substrate whose surfaces have a second bonding layer and electrodes. The first bonding layer is combined with the second bonding layer, and the metal pads are in electrical communications with the electrodes. The second substrate may be a flexible substrate to decrease the strain between the first substrate and the second substrate.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: July 3, 2007
    Assignee: Industrial Technology Research Institute
    Inventor: Su-Tsai Lu
  • Patent number: 7226653
    Abstract: A printed circuit board for an electronic circuit, especially for the ultra-high frequencies located in the GHz range that comprises at least one conductor layer, which is arranged on top of an insulating layer and which is flatly joined to said insulating layer. Improved mechanical, thermal and electrical properties are attained by virtue of the fact that the insulating layer is a thin glass layer.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: June 5, 2007
    Assignee: PPC Electronic AG
    Inventors: Peter Straub, Peter Weber
  • Patent number: 7226654
    Abstract: A laminated wiring board comprising: a first wiring board forming wiring layers on the upper surface and on the lower surface of a first ceramic insulated substrate; and a second wiring board forming wiring layers on the upper surface and on the lower surface of a second ceramic insulated substrate; the wiring layer on the lower surface of the first wiring board and the wiring layer on the upper surface of the second wiring board being connected together through connecting electrodes; wherein a coefficient ?1 of thermal expansion of the first ceramic insulated substrate at 0 to 150° C. and a coefficient ?2 of thermal expansion of the second ceramic insulated substrate at 0 to 150° C. are satisfying the following conditions: ?1<?2 ?2??1?9×10?6/° C.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: June 5, 2007
    Assignee: Kyocera Corporation
    Inventors: Shinya Kawai, Masanari Kokubu, Youji Furukubo
  • Patent number: 7223481
    Abstract: An object of the present invention is to produce an ultra-thin copper foil with a carrier which has few pinholes and small surface roughness and which has an the thickness of less than 5 ?m, and to produce the method of producing the foil, and further to produce a printed circuit board for fine pattern, a multilayer printed circuit board and a chip on film circuit board by using the ultra-thin copper foil with a carrier. The present invention provides an ultra-thin copper foil with a carrier produced by stacking a peeling layer and an ultra thin copper foil in order on the surface of a carrier copper foil which is made smooth so that the mean surface roughness of at least one side is Rz of 0.01 to 2.0 ?m by the chemical polishing, the electrochemical dissolution, or the smoothing plating processing method independently, combining two or more, or further combining the mechanical polishing.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 29, 2007
    Assignee: Furukawa Circuit Foil Co., Inc.
    Inventors: Yuuji Suzuki, Akira Matsuda
  • Patent number: 7214419
    Abstract: A conductive paste is provided, which has good conductivity and good adhesiveness to substrates and has good long-lasting stability of these properties, and which, when applied to a through-hole of a multi-layered substrate, ensures improved reliability of bonding to the end faces of conductive layers in the through-hole. Therefore, the paste does not require through-hole plating. The conductive paste comprises (A) 100 parts by weight of a resin component that contains an acrylate resin and an epoxy resin, (B) from 200 to 1800 parts by weight of a metal powder of at least two metals that contain at least one low-melting-point metal having a melting point of not higher than 180° C. and at least one high-melting-point metal having a melting point of not lower than 800° C., (C) from 0.5 to 40 parts by weight of a curing agent that contains from 0.3 to 35 parts by weight of a phenol-type curing agent, and (D) from 0.3 to 80 parts by weight of a flux.
    Type: Grant
    Filed: May 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Tatsuta Electric Wire & Cable Co., Ltd.
    Inventors: Hiroaki Umeda, Hisatoshi Murakami, Kiyoshi Iwai
  • Patent number: 7208218
    Abstract: A method of providing a resistance to oxidation of Nickel at high temperatures by combining Ni powder with five percent Pt resinate, and heating the same to a temperature of 500° C. to 1300° C. Electro-conductive components serving as electrodes and the like comprise a Ni/Pt powder subjected to temperatures of between 500° C. and the respective melting points of Ni and Pt.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: April 24, 2007
    Assignee: Vishay Vitramon Incorporated
    Inventor: Vito A. Coppola
  • Patent number: 7205482
    Abstract: Electric conductor patterns having inner leads arranged at a pitch of not larger than 60 ?m are formed on a front surface of an insulating layer of a tape carrier for TAB. A reinforcing layer of stainless steel foil is formed on a rear surface of the insulating layer so as to be extend along a lengthwise direction at opposite side edge portions in a widthwise direction of the insulating layer. Accordingly, both dimensional accuracy and positional accuracy can be improved at the time of carrying the tape carrier for TAB or at the time of mounting and bonding electronic parts though the insulating layer can be formed so as to be thin.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: April 17, 2007
    Assignee: Nitto Denko Corporation
    Inventors: Toshiki Naito, Hiroshi Yamazaki, Toshihiko Omote
  • Patent number: 7199456
    Abstract: The invention relates to an injection moulded product comprising an attached body which has been attached by an intermediate layer. The body has been attached to the injection moulded product by an intermediate layer attached to the body prior to the injection moulding. The invention also relates to a method for the manufacture of an injection moulded product comprising a body which has been attached by an intermediate layer.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 3, 2007
    Assignee: Rafsec Oy
    Inventors: Anu Krappe, Samuli Strömberg
  • Patent number: 7192654
    Abstract: The invention concerns multilayered constructions useful for forming resistors and capacitors, for the manufacture of printed circuit boards or other microelectronic devices. The multilayered constructions comprise sequentially attached layers comprising: a first electrically conductive layer, a first thermosetting polymer layer, a heat resistant film layer, a second thermosetting polymer layer, and a nickel-phosphorus electrical resistance material layer electroplated onto a second electrically conductive layer.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: March 20, 2007
    Assignees: Oak-Mitsui Inc., Ohmega Technologies Inc.
    Inventors: John A. Andresakis, Pranabes K. Pramanik, Bruce Mahler, Daniel Brandler
  • Patent number: 7189449
    Abstract: In a metal/ceramic bonding substrate 10 wherein a circuit forming metal plate 14 is bonded to one side of a ceramic substrate 12 and a radiating metal base plate 16 is bonded to the other side thereof, a difference in level is provided along the entire circumference of the bonding surface of the ceramic substrate 12 to the metal base plate 16. The difference in level is provided by forming at least one of a rising portion 16a and a groove portion 116b on and in the metal base plate 16.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: March 13, 2007
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Hideyo Osanai, Takayuki Takahashi, Makoto Namioka
  • Patent number: 7182996
    Abstract: Processes for depositing nanowires on a substrate and nanowire-based devices that can be formed using these processes are described. In one embodiment, a process includes forming an organic layer on an electrically conductive layer formed on the substrate. The organic layer includes a first region and a second region. The first region has an affinity for the nanowires and is electrically conductive. The process also includes contacting the organic layer with a composition including the nanowires dispersed in a compatible solvent for a time sufficient to selectively deposit at least one of the nanowires on the first region of the organic layer.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: February 27, 2007
    Assignee: Florida State University Research Foundation, Inc.
    Inventor: Seunghun Hong
  • Patent number: 7179519
    Abstract: Polyimide/metal laminates having a polyimide film and a metal layer laminated thereon, wherein the polyimide film contains titanium element and flexible print wiring boards with the use of the same are disclosed. The polyimide/metal laminates are excellent in adhesion under the ordinary conditions and, moreover, can sustain the adhesive strength at a high ratio after exposure to high temperature or high temperature and high humidity. Owing to these characteristics, these polyimide/metal laminates are appropriately usable in flexible print wiring boards, multi-layered print wiring boards, rigid flex wiring boards, tapes for TAP, semiconductor packages such as CFOs and multi chip modules (MCMs), magnetic recording films, coating films for aerospace materials and filmy resistance elements.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: February 20, 2007
    Assignee: Kaneka Corporation
    Inventors: Masaru Nishinaka, Kiyokazu Akahori
  • Patent number: 7179520
    Abstract: A circuit substrate is described where the circuit substrate has a first wiring group extending in a first direction and a second wiring group extending in a second direction substantially orthogonal to the first direction. The first wiring group of the circuit substrate is stronger than the second wiring group, and the second wiring group bends more easily than the first wiring group, which results in directional flexibility of said circuit substrate.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: February 20, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takayuki Saeki
  • Patent number: 7180006
    Abstract: A tape substrate including an insulating film, a copper foil pattern formed on the insulating film at one side of the insulating film, and provided with a connecting area where an electronic element is to be mounted, a barrier layer plated on the copper foil pattern at the connecting area, and formed with a plurality of pores, and a tin layer plated on the barrier layer, and alloyed with a portion of the copper foil pattern corresponding to the connecting area, through the pores. A method for fabricating the tape substrate is also disclosed. In accordance with the invention, it is possible to reduce the time taken for the copper foil pattern to come into contact with the electroless tin plating solution used in the tin plating process, thereby preventing the copper component of the copper foil pattern from being eluted. Accordingly, there is no open-circuit fault caused by formation of pores.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: February 20, 2007
    Assignees: LG Electronics Inc., LG Micron Co., Ltd.
    Inventors: Soon Bog Kwon, Sang Hun Lee, Yang Sik Moon, Ki Pyo Hong, Yoon Kuen Cho
  • Patent number: 7175920
    Abstract: The present invention is to provide an ultra-thin copper foil with a carrier which comprises a release layer, a diffusion preventive layer and a copper electroplating layer laminated in this order, or a diffusion preventive layer, a release layer and a copper electroplating layer laminated in this order on the surface of a carrier foil, wherein a surface of the copper electroplating layer is roughened; a copper-clad laminated board comprising the ultra-thin copper foil with a carrier being laminated on a resin substrate; a printed wiring board comprising the copper-clad laminated board on the ultra-thin copper foil of which is formed a wiring pattern; and a multi-layered printed wiring board which comprising a plural number of the above printed wiring board being laminated.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: February 13, 2007
    Assignee: Circuit Foil Japan Co., Ltd.
    Inventors: Akitoshi Suzuki, Shin Fukuda, Kazuhiro Hoshino, Tadao Nakaoka
  • Patent number: 7177519
    Abstract: A functional multilayer film and a method for manufacturing the same is provided in which the intervals of fine metallic bodies in the thickness direction and the arrangement thereof in the surface direction are regular, and the fine metallic bodies arranged on each layer are aligned in the thickness direction. A functional multilayer film is obtained by fixing a plurality of fine metallic bodies to a matrix made of a dielectric substance. The matrix is obtained by laminating metal-arranged thin films, which each contain a dielectric thin film having a predetermined thickness and the fine metallic bodies arranged on the dielectric thin film. A plurality of recesses is regularly formed on the surface of the dielectric thin film, and the fine metallic bodies are arranged in the lower parts of the recesses.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: February 13, 2007
    Assignees: Alps Electric Co., Ltd.
    Inventors: Yoshihiro Someno, Munemitsu Abe, Masayoshi Esashi
  • Patent number: 7172805
    Abstract: A method for manufacturing a mid-plane. a multi-layer board having a connection assembly is provided and a dielectric layer with a channel formed therein to define a perimeter of a connector area is provided. The dielectric layer is bonded to the multi-layer board such that the connector area overlaps the part of the connection assembly of the multi-layer board. At least a portion of the connector area in the dielectric layer is removed to expose the connection assembly of the multi-layer board. A rigid multilayer is also disclosed. The rigid multilayer includes a multi-layer board and a dielectric layer. The multi-layer board has a connection assembly. The dielectric layer has a channel formed therein to define a perimeter of a connector area. The dielectric layer is bonded to the multi-layer board such that the connector area overlaps the connection assembly of the multi-layer board. The connector area can then be removed such as by depth controlled routing.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: February 6, 2007
    Assignee: Viasytems Group, Inc.
    Inventors: Gerald A. J. Hermkens, Marcel Smeets, Roger Theelen, Peter J. M. Thoolen, Frank Speetjens
  • Patent number: 7172806
    Abstract: A sintered ceramic has a porosity of greater than about 30 percent and less than about 80 percent by volume. Pores are filled with an epoxy resin. A filling factor of the epoxy resin is about 40 percent by volume or more. A monolithic ceramic electronic component having an inner electrode, for example, a chip inductor is manufactured with such a porous sintered ceramic. When a direct current is superimposed, the resulting monolithic ceramic electronic component has a substantially unchanged self-resonant frequency and also has a rate of decrease in impedance of about 50 percent or less at 100 MHz.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 6, 2007
    Assignee: Murata Manufacturing Co.
    Inventors: Tomoo Takazawa, Takehiko Otsuki, Toshio Kawabata, Kaoru Tachibana
  • Patent number: 7161117
    Abstract: A window glass for vehicles equipped with a conductor, which comprises a glass plate, a patterned conductor layer formed on the glass plate, and a covering layer formed to cover the conductor layer, wherein the covering layer comprises a fired product obtained by firing a composition containing a crystalline glass powder and a reducing agent capable of reducing silver ions.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: January 9, 2007
    Assignee: Asahi Glass Company, Limited
    Inventors: Toshio Minowa, Hiroyuki Hayakawa, Shuji Taguchi
  • Patent number: 7160628
    Abstract: A substrate with a patterned opaque coating formable into an opaque aperture in one process is provided. The opaque coating includes at least a bottom layer and a top layer. The bottom and top layers each include a material selected from the group consisting of chrome and chrome oxide. The top layer has a compressive stress, which makes the opaque coating more resistant to pinhole formation during downstream processing.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: January 9, 2007
    Assignee: Corning Incorporated
    Inventors: Robert Bellman, Ljerka Ukrainczyk