Patents Examined by Chandra Chaudhari
  • Patent number: 10249631
    Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 2, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chien-Sheng Su, Feng Zhou, Jeng-Wei Yang, Hieu Van Tran, Nhan Do
  • Patent number: 10249435
    Abstract: The invention relates to an electronic component. The electronic component 2 has an electrical assembly 3 having two electrical connections 4, 5 that are each formed on opposing faces of the assembly. For each connection 4, 5, the component has at least one electrically conductive connection element 9, 10 having a mounting foot 14, 15 for connection to a circuit carrier 22. According to the invention, the connection element 8, 9 has at least two metal layers 10, 11, 12, 13 at least on one section, wherein the metal layers are each formed from different metals and integrally connected to one another. Preferably, one metal layer 12, 13 from the metal layers has greater thermal conductivity than the other metal layer 10, 11.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: April 2, 2019
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Peuser
  • Patent number: 10243073
    Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Steven Bentley, Kwan-Yong Lim, Hiroaki Niimi, Junli Wang
  • Patent number: 10229961
    Abstract: A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a thin film transistor provided on a first side of the substrate; a first electrode connected with the thin film transistor; an organic emission layer provided on the first electrode and emitting light; a second electrode provided on the organic emission layer; and a light blocking layer contacting the substrate from a second side that faces the first side of the substrate, wherein the light is emitted in a direction toward the second electrode from the organic emission layer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Wan Choi, Young Bin Kim
  • Patent number: 10229975
    Abstract: A method includes forming an oxide layer on a silicon-germanium (SiGe) fin formed on a substrate. The first oxide layer comprises a mixture of a germanium oxide compound (GeOx) and a silicon oxide compound (SiOx). The first oxide layer is modified to create a Si-rich outer surface of the SiGe fin. A silicon nitride layer is deposited on the modified first oxide layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • Patent number: 10224302
    Abstract: Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventor: Xinhua Wang
  • Patent number: 10217686
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: February 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Walid M. Meliane, Kevin J. Anderson, Tarak A. Railkar
  • Patent number: 10217685
    Abstract: The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, and a top electronic component. The bottom substrate includes a bottom signal via extending through the bottom substrate and the top substrate includes a top signal via extending through the top substrate. The perimeter wall extends between a periphery of the top substrate and a periphery of the bottom substrate to form a cavity. The bottom electronic component is mounted on the bottom substrate, exposed to the cavity, and electrically coupled to the bottom signal via. The top electronic component is mounted on the top substrate, exposed to the cavity, and electrically coupled to the top signal via.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Kevin J. Anderson, Ning Chen
  • Patent number: 10217839
    Abstract: Disclosed is a field effect transistor (FET) with a replacement metal gate (RMG) and a method of forming the FET. The RMG includes a conformal gate dielectric layer and a stack of gate conductor layers on the gate dielectric layer. The stack includes a conformal work function metal (WFM) layer and a conductive fill material (CFM) layer on the WFM layer. Within the stack, the top surface of the CFM layer is above the level of the top of an adjacent vertical portion of the WFM layer. A dielectric gate cap has a center portion and an edge portion. The center portion is above the top surface of the CFM layer and the edge portion is above the top of the adjacent vertical portion of the WFM layer and is further positioned laterally immediately adjacent to an upper portion of an outer sidewall of the CFM layer.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: February 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Kisup Chung, Victor Chan, Koji Watanabe
  • Patent number: 10204963
    Abstract: The present invention provides an LED chip including a light-emitting layer, a P electrode, an N electrode, an anode and a cathode, the N electrode, the light-emitting layer and the P electrode are sequentially stacked, the P electrode is electrically connected to the anode, the N electrode is electrically connected to the cathode, the light-emitting layer includes multiple color light-emitting layers whose colors differ from each other, and the multiple color light-emitting layers are provided in a same layer, and electrically connected to the anode through the P electrode and to the cathode through the N electrode. The present invention further provides an LED, a backlight source and a display apparatus. When an LED including the LED chip is used as a backlight source of a liquid crystal display apparatus, performance ability of the display apparatus on a plurality of colors can be improved during image display.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: February 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BOE OPTICAL SCIENCE AND TECHNOLOGY CO., LTD.
    Inventor: Tao Wang
  • Patent number: 10204788
    Abstract: A method of forming a high dielectric constant (high-k) dielectric layer by atomic layer deposition includes the following steps. Cycles are performed one after another, and each of the cycles sequentially includes performing a first oxygen precursor pulse to supply an oxygen precursor to a substrate disposed in a reactor; performing a first oxygen precursor purge after the first oxygen precursor pulse; performing a chemical precursor pulse to supply a chemical precursor to the substrate after the first oxygen precursor purge; and performing a chemical precursor purge after the chemical precursor pulse. The first oxygen precursor pulse, the first oxygen precursor purge, the chemical precursor pulse, and the chemical precursor purge are repeated by at least 3 cycles. A second oxygen precursor pulse is performed to supply an oxygen precursor to the substrate after the cycles. A second oxygen precursor purge is performed after the second oxygen precursor pulse.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shan Ye, Shih-Cheng Chen, Tsuo-Wen Lu, Tzu-Hsiang Su, Po-Jen Chuang
  • Patent number: 10199363
    Abstract: A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Tsukada, Masayuki Honda, Yoshihisa Fukushima, Scott Richard Cyr
  • Patent number: 10181427
    Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Kyun Song, Yoon Tae Hwang, Kyu Min Lee, Soo Jung Choi
  • Patent number: 10163626
    Abstract: An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Huei Lin, Yen-Yu Chen, Chih-Pin Tsao, Shih-Hsun Chang
  • Patent number: 10164090
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer provided with a gate trench, a first conductivity type source region formed to be exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to a back surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region closer to the back surface of the semiconductor layer to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and a gate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench so that a channel is formed in operation and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 25, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Kengo Omori
  • Patent number: 10162440
    Abstract: An array substrate, a touch display apparatus and a test method thereof are provided. The array substrate can include a substrate, a common electrode structure and a conductive structure for testing. The common electrode structure and conductive structure can be arranged on a same side of the substrate. The common electrode structure can be insulated from the conductive structure for testing. There can be an overlapping area between a projection of the common electrode structure and a projection of the conductive structure for testing in a direction perpendicular to the substrate. Laser melting may be performed on the overlapping area to electrically connect the common electrode structure to the conductive structure for testing.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: December 25, 2018
    Assignees: Shanghai Avic OPTO Electronics Co., Ltd., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Huijun Jin
  • Patent number: 10153239
    Abstract: A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with the metal ring, encapsulating the device die and the metal ring in an encapsulating material. The method further includes filling a dielectric material into a space encircled by the metal ring, and forming a second metal plate covering the dielectric material and the metal ring, with an opening formed in the second metal plate. A plurality of redistribution lines is formed, with one of the redistribution lines overlapping a portion of the opening. The first metal plate, the metal ring, the second metal plate, and the dielectric material in combination form an antenna or a waveguide. The redistribution line forms a signal-coupling line of the passive device.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Jeng-Shien Hsieh, Wei-Heng Lin
  • Patent number: 10147715
    Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-hsin Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu
  • Patent number: 10134880
    Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 20, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, Alvin J. Joseph, Pernell Dongmo
  • Patent number: 10128245
    Abstract: Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are on a semiconductor substrate, a first gate structure between the first active regions, and first contacts connected to the first active regions, respectively; and a second semiconductor element including second active regions that are doped with a second conductivity-type impurity different from the first conductivity-type impurity and that are on the semiconductor substrate, a second gate structure between the second active regions, and second contacts connected to the second active regions, respectively, and having a second length greater than a first length of each of the first contacts in a first direction parallel to an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do Sun Lee, Joon Gon Lee, Na Rae Kim, Chul Sung Kim, Do Hyun Lee, Ryuji Tomita, Sang Jin Hyun