Patents Examined by Charles Bowers
  • Patent number: 6395564
    Abstract: The invention provides a method for fabricating a light-emitting diode with uniform color temperature, comprising the steps of: forming a plurality of light-emitting diodes on a wafer; obtaining the light emission wavelengths of the light-emitting diodes on the wafer; and forming different doses of phosphor on the corresponding light-emitting diode on the wafer according to the light emission wavelengths of respective light-emitting diodes. Finally, the light-emitting diodes on the wafer emit light with uniform color temperature.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: May 28, 2002
    Assignee: Arima Optoelectronics Corp.
    Inventor: Wen-Chieh Huang
  • Patent number: 6395633
    Abstract: A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: May 28, 2002
    Assignee: World Wiser Electrics Inc.
    Inventors: Jao-Chin Cheng, Chang-Chin Hsieh, Chih-Peng Fan, Chin-Chung Chang
  • Patent number: 6396076
    Abstract: A test structure determines the trench depth from etching in a resistive substrate. The test structure has a first contact and a second contact to the substrate. Between the first and second contact is disposed an etch window. A measurement of resistance between the first contact and the second contact is indicative of the depth of etching in the etch window.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: May 28, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Dennis W. Tom
  • Patent number: 6395649
    Abstract: Polyorganosilicon dielectric coatings are prepared by subjecting specified polycarbosilanes to thermal or high energy treatments to generate cross-linked polyorganosilicon coatings having low k dielectric properties. The thermal process includes multi-step sequentially increasing temperature heating steps. The instantly prepared polyorganosilicon polymers can be employed as dielectric interconnect materials and film coatings for conductor wiring in semiconductor devices. These polyorganosilicon film coatings have the additional characteristics of relative thermal stability and excellent adhesion to substrate surfaces.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: May 28, 2002
    Assignee: Honeywell International Inc.
    Inventor: Hui-Jung Wu
  • Patent number: 6391797
    Abstract: A method of manufacturing a semiconductor device, comprises the following steps of growing a dielectric film made of a dielectric material whose dielectric constant is improved by crystallization thereof, on a semiconductor substrate to utilize the dielectric film as a capacitor film, and applying a voltage to the semiconductor substrate in a plasma atmosphere to increase a grown interface temperature by “dielectric heating” upon growth of the dielectric film
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: May 21, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinobu Takehiro, Satoshi Yamauchi, Masaki Yoshimaru
  • Patent number: 6391668
    Abstract: The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: May 21, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Carlos M. Chacon, Sundar S. Chetlur, Brian E. Harding, Minesh A. Patel, Pradip K. Roy
  • Patent number: 6391700
    Abstract: A pad oxide layer is formed on a substrate, wherein the thickness of the pad oxide layer is about greater than 250 Å. The alignment photo-resist layer is selectively patterned by a conventional lithography method to define the N-well region. The pad oxide layer is partially etched by using etch method with the alignment photo-resist pattern as a mask until the thickness of the pad oxide layer is about 100 Å to form an alignment mark. The N-type ion-implant is performed by the alignment photo-resist pattern as a mask to form an N-doped region in the substrate. Then, the alignment photo-resist pattern is removed. The P-well photo-resist is defined and formed on the pad oxide layer, then performing a P-type ion-implant through the pad oxide layer into the substrate by means of the P-well photo-resist as a mask to form a P-doped region. Then remove the P-well photo-resist and proceed with the drive-in process to form the N-well region and P-well region.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventor: Kuen-Shyi Tsay
  • Patent number: 6391759
    Abstract: A bonding method which prevents wire sweep and the wire structure thereof mainly provide the pre-shifted wire between the first bonding point and the second bonding point and counter to the mold flow from the side thus intensifying the strength of the wire structure and increasing the deformation space of the wire sustaining mold flow.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: May 21, 2002
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Te-Tsung Chao, Hui-Chin Fang
  • Patent number: 6391805
    Abstract: This invention embodies an improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduce the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: May 21, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Richard H. Lane, Phillip G. Wald
  • Patent number: 6391667
    Abstract: A power supply unit which supplies voltage to electric components, includes: a DC power supply (40) which supplies DC voltage to the electric components; at least one capacitor (C1), provided between the DC power supply (40) and the electric components, which charges the DC voltage; an input switch (SW1a) which connects or disconnects the capacitor (C1) and the DC power supply (40); and an output switch (SW1b) which connects or disconnects the capacitor (C1) and the electric components (semiconductor device under test); and a switching control unit (60) which charges the capacitor (C1) and supplies the DC voltage charged in the capacitor (C1) to the electric components. Thereby, the DC voltage to be supplied to the electric components or semiconductor device under test can be temporarily switched to low-noise DC voltage supplied from the charged-up capacitor (C1) during the test.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: May 21, 2002
    Assignee: Advantest Corporation
    Inventor: Yoshihiro Hashimoto
  • Patent number: 6391742
    Abstract: A small size electronic part comprises a silicon substrate having a functional element and a signal output portion to output a signal from the functional element to outside the electronic part; a glass substrate provided on the silicon substrate such that the signal output portion of the silicon substrate is in contact with the glass substrate; a communicating hole provided in the glass substrate and at least a portion of the signal output portion of the silicon substrate so as to pass through the glass substrate and cut into at least a part of the signal output portion; and a conductive film provided on an inner wall surface of the communicating hole and extending on a surface of the glass substrate.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: May 21, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hiroshi Kawai
  • Patent number: 6391687
    Abstract: A semiconductor device including a substantially flat leadframe that includes a die attach area on a surface of the leadframe. A die including solder bumps is placed thereon and a plurality of columns surround at least a portion of the periphery of the die attach area. The die is positioned within the die attach area and the columns have a height substantially equal to the solder bumps and the die on the leadframe.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: May 21, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Elsie A. Cabahug, Consuelo Tangpuz
  • Patent number: 6391744
    Abstract: A method of thinning a non-SOI device using an SOI thinning process that includes the steps of receiving an SOI starting wafer, where the SOI starting wafer includes a silicon substrate and an oxide layer thereon; selecting a non-SOI fabrication process for fabricating the non-SOI device; forming a layer of device quality silicon on the oxide layer of the SOI starting wafer to a sufficient thickness and doping profile to realize the non-SOI device; fabricating the non-SOI device in the device quality silicon layer using the non-SOI fabrication process selected; forming a support layer on the device quality silicon layer having the non-SOI device fabricated therein; and thinning the result of the last step using the SOI thinning process.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: May 21, 2002
    Assignee: The United States of America as represented by the National Security Agency
    Inventors: John J. Hudak, Thomas R. Neal, Pramod Chintaman Karulkar
  • Patent number: 6391769
    Abstract: A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: May 21, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-myeong Lee, Hyun-seok Lim, Byung-hee Kim, Gil-heyun Choi, Sang-in Lee
  • Patent number: 6391760
    Abstract: A method of forming a local interconnect is provided. A semiconductor is provided. An isolation structure, a transistor and a conductive layer are formed on the substrate. A dielectric layer with an opening is formed over the substrate. A part of the dielectric layer is removed by a photolithography and etching process to form a via opening to expose a part of the gate of the transistor or a part of the conductive layer. A conformal barrier layer is formed in the via opening and overflows the dielectric layer. A conductive plug is formed in the via opening. The barrier layer is patterned to form a local interconnect.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 21, 2002
    Assignee: United Microelectronics Corp.
    Inventors: C. C. Hsue, Wei-Chung Chen
  • Patent number: 6391774
    Abstract: A fabrication process of a semiconductor device can bury Cu within a wiring groove and a grain is large. A fabrication process of a semiconductor device, in which wiring is formed on the semiconductor substrate, includes a first step of depositing a first conductive film on the substrate via an insulation film, a second step, subsequent to the first step, of depositing a second conductive film having film thickness thicker than the film thickness of the first conductive film, on the first conductive film, a third step following the second step, of performing heat treatment at least for the first and second conductive films, and a fourth step following the third step, of forming wiring by shaping the conductive films after the heat treatment.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: May 21, 2002
    Assignee: NEC Corporation
    Inventor: Toshiyuki Takewaki
  • Patent number: 6391741
    Abstract: A process for assembling a microactuator on a R/W transducer that includes forming a first wafer of semiconductor material having a plurality of microactuators including suspended regions and fixed regions separated from each other by first trenches; forming a second wafer of semiconductor material comprising blocking regions connecting mobile and fixed intermediate regions separated from each other by second trenches; bonding the two wafers so as to form a composite wafer wherein the suspended regions of the first wafer are connected to the mobile intermediate regions of the second wafer, and the fixed regions of the first wafer are connected to the fixed intermediate regions of the second wafer; cutting the composite wafer into a plurality of units; fixing the mobile intermediate region of each unit to a respective R/W transducer; and removing the blocking regions. The blocking regions are made of silicon oxide, and the intermediate regions are made of polycrystalline silicon.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: May 21, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Sarah Zerbini, Simone Sassolini, Benedetto Vigna
  • Patent number: 6387724
    Abstract: An ion-sensitive sensor has an active layer of silicon with source and drain diffusion regions of a field-effect transistor formed therein, patterned layers of silicon oxide and metal on one side of the active silicon layer, and a layer of insulative support material on the metal and silicon oxide layers. A continuous layer of silicon oxide on the other side of the active silicon layer has an exposed surface in the region of the field-effect transistor so that surface charge is formed in the exposed area of the continuous silicon oxide layer when placed in contact with an electrolyte solution. The surface charge induces a channel in the undiffused channel region between the source and drain regions, enabling the flow of current between source and drain contacts under proper bias conditions.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: May 14, 2002
    Assignee: Dynamics Research Corporation
    Inventor: Howard W. Walker
  • Patent number: 6387776
    Abstract: A method for forming trench isolation regions in a semiconductor device reliably electrically isolates a device and enhances a device density. The method for forming trench isolation regions includes forming a trench on a surface of a semiconductor device with a predetermined depth; forming a nitride liner layer on the surface of the semiconductor including the trench, forming a gas distribution region which is uniformly distributed on the nitride liner layer; and forming an insulation layer by filling the trench after said forming of the gas distribution region. The gas distribution region is preferably formed by introducing an ozone gas. The insulation layer is preferably formed by simultaneously introducing ozone gas and TEOS(Tetra Ethyl Ortho-Silicate) chemical.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seung Yi, Tae Wook Seo, Jin-Ho Jeon
  • Patent number: 6387729
    Abstract: A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: May 14, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Teng Eng, Min Yu Chan, Jing Sua Goh, Siu Waf Low, Boon Pew Chan, Tuck Fook Toh, Chee Kiang Yew, Pak Hong Yee