Patents Examined by Charles Bowers
  • Patent number: 6380041
    Abstract: An ultra-large scale integrated circuit semiconductor device having a laterally non-uniform channel doping profile is manufactured by using a Group IV element implant at an implant angle of between 0° to 60° from the vertical to create interstitials in a doped silicon substrate under the gate of the semiconductor device. After creation of the interstitials, a channel doping implantation is performed using a Group III or Group V element which is also implanted at an implant angle of between 0° to 60° from the vertical. A rapid thermal anneal is then used to drive the dopant laterally into the channel of the semiconductor device by transient enhanced diffusion.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Geoffrey Choh-Fei Yeap, Ognjen Milic, Che-Hoo Ng
  • Patent number: 6380037
    Abstract: A method of manufacturing a line type or area type image sensor integrated circuit device with a high resolution is provided. In a semiconductor integrated circuit device using an SOI substrate, a signal processing circuit is formed in an SOI region while a photodiode is formed in a bulk region to have a trench structure in which a diffusion layer is formed on the side walls and the bottom of the trench, and the inside of the trench is coated with an insulting film, or an insulating film and polycrystalline silicon provided with an electric potential. With such a manufacturing method, a semiconductor integrated circuit device mounting a photodiode showing sufficient S/N ratio is provided despite of its small cell size.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: April 30, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Jun Osanai
  • Patent number: 6380071
    Abstract: A method of fabricating a semiconductor device, which forms dielectric sidewalls reliably at each side of a first wiring structure to protect its conductive line in the etching process for forming a via hole in an interlayer dielectric layer to cover the first wiring structure. In this method, the first wiring structure is formed on a first dielectric layer. A second dielectric layer is formed on the first dielectric layer to cover the first wiring structure. A third dielectric layer serving as an interlayer dielectric layer is formed on the second dielectric layer. The third and second dielectric layers are polished using the CMP technique until the dielectric of the first wiring structure is exposed, thereby leaving part of the second dielectric layer that extends along each side of the first wiring structure and the surface of the first dielectric layer. The dielectric layer is etched using a mask to form a via hole. The hole is then filled with a conductive plug.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: April 30, 2002
    Assignee: NEC Corporation
    Inventor: Takuji Onuma
  • Patent number: 6379984
    Abstract: A high-precision etalon and novel method of construction thereof is presented. The etalon comprises a pair of plane-parallel flat mirrors spaced a first distance apart, a pair of plane-parallel spacers transversely attached to the pair of mirrors which operate to fix the first distance between the pair of mirrors, and a thin film mirror layer deposited on at least one of the pair of plane-parallel flat mirrors to form a laser cavity therein of a precise second distance apart. The method of constructing an etalon in accordance with the invention includes the steps of fabricating one or more spacers, measuring the length of the spacer(s), and deriving a dimensional deviation of the spacer length from a nominal cavity dimension specified for the etalon. A thin-film pedestal is then deposited on one, the other, or both of a first and second substrate and then coated with a reflective coating. The etalon is then assembled using the spacer(s) and first and second substrates.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: April 30, 2002
    Assignee: Research Electro-Optics, Inc.
    Inventors: Jon C. Sandberg, Ramin Lalezari
  • Patent number: 6380057
    Abstract: Nickel salicide processing is implemented by implanting nickel into the active regions, prior to depositing Ni, to catalyze the reaction of Ni and Si during annealing to form a NiSi layer on the polysilicon gate electrodes and source/drain regions without the formation of rough interfaces between the nickel silicide layers and underlying silicon and without conductive bridging between the metal silicide layer on the gate electrode and the metal silicide layers on associated source/drain regions, particularly in the presence of silicon nitride sidewall spacers.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: April 30, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew S. Buynoski, George Jonathan Kluth, Paul R. Besser, Paul L. King
  • Patent number: 6380557
    Abstract: A test chip for a molding material including fillers, including, a semiconductor substrate and a test circuit formed on the substrate. The test circuit includes at least one transistor, and two dams formed on the substrate for providing a slit therebetween, the slit capturing the fillers of the molding material when the molding material is applied to the test circuit. A method for testing a molding material including fillers for a semiconductor device, including steps of preparing a test chip, placing the test chip in molding equipment, injecting the molding material including fillers into the molding equipment, capturing the fillers in the slit, and detecting the influence of the fillers on electrical characteristics of the test chip using the test circuit.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: April 30, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masaru Takahara
  • Patent number: 6380565
    Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of a first conductivity type having a front surface and a rear surface, including a first main vertical thyristor, the rear surface layer of which is of the second conductivity type, a second main vertical thyristor, the rear surface layer of which is of the first conductivity type. A structure for triggering each of the first and second main thyristors is arranged to face regions mutually distant from the two main thyristors, the neighboring portions of which correspond to a region for which, for the first main thyristor, a short-circuit area between cathode and cathode gate is formed.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 30, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Franck Duclos, Jean-Michel Simonnet, Olivier Ladiray
  • Patent number: 6379991
    Abstract: The invention includes a semiconductor processing method of forming a die package. An insulative substrate is provided. Circuitry is over a topside of the substrate, and a slit extends through the substrate. A semiconductive-material-comprising die is provided beneath the substrate, and has a surface exposed through the slit in the substrate. The die has an edge. There is a gap between the die and an underside of the substrate. A radiation-curable material is injected through this slit and into the gap. Radiation is directed from over the edge to the gap to cure at least a portion of the radiation-curable material within the gap and thus form a dam which impedes non-cured radiation-curable material from flowing beyond the edge.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: April 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Ford B. Grigg, Joseph M. Brand
  • Patent number: 6379992
    Abstract: A method capable of enhancing the uniformity of the color filter array and removing scum deposits from the surface of the color filter array to improve the yield ratio of the device is disclosed.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: April 30, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventor: Wan-Hee Jo
  • Patent number: 6380061
    Abstract: A method forwarding a semiconductor device that is excellent in bonding strength of bumps with respective protruded electrodes and having high reliability. A wiring pattern 28 to be connected to an electrode 22 of a semiconductor chip 20 is formed on an insulting film 23 formed on the semiconductor chip 20 in which the electrode 20 is formed. Protruded electrodes 32 are formed on the wiring pattern 28. The wiring pattern 28 is covered with a protective film 36, and a bump 38 for external connection is formed on the end portion of each of the protruded electrodes 32 exposed from the protective film 36. The bump 38 is formed in such a manner that the bump is bonded to the at least entire end face of each of the protruded electrodes 32.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: April 30, 2002
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Syoichi Kobayashi, Naoyuki Koizumi, Osamu Uehara, Hajime Iizuka
  • Patent number: 6380045
    Abstract: A fabrication method for forming asymmetric wells of a DRAM cell, and more particularly to a fabrication method for producing a transistor that is capable of reducing body effect, gate-swing and junction leakage current so as to enhance the reliability of a DRAM device. After doped regions used for source/drain are formed in a substrate, a local well and an anti-punchthrough pocket are then formed under the doped region to be used as drains in order to prevent short channel effect. Because the local well and the anti-punchthrough pocket do not extend to the doped region that is used as a source, the DRAM cell's ability for charge retention therefore can be kept at the same time.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: April 30, 2002
    Assignee: Vanguard International Semiconductor Corp.
    Inventor: Jyh-Chyum Guo
  • Patent number: 6380103
    Abstract: At least both a rapid thermal etch step and a rapid thermal oxidation step are performed on a semiconductor substrate in situ in a rapid thermal processor. A method including an oxidation step followed by an etch step may be used to remove contamination and damage from a substrate. A method including a first etch step followed by an oxidation step and a second etch step may likewise be used to remove contamination and damage, and a final oxidation step may optionally be included to grow an oxide film. A method including an etch step followed by an oxidation step may also be used to grow an oxide film. Repeated alternate in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is accomplished.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: April 30, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Randhir P. S. Thakur
  • Patent number: 6380036
    Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: April 30, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hidekazu Oda, Shuichi Ueno, Takehisa Yamaguchi
  • Patent number: 6380074
    Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: April 30, 2002
    Assignee: Infineon Technologies AG
    Inventors: Markus Kirchhoff, Hans-Peter Sperlich, Uwe Schilling, Zvonimir Gabric, Oswald Spindler, Stephan Wege, Hans Glawischnig
  • Patent number: 6380009
    Abstract: A method of manufacturing a top-gate self-aligned thin film transistor involves the use of back exposure of a negative resist (26) using the lower source and drain electrode pattern (11, 12) as a photomask. A transparent amorphous silicon layer (24) is used as the gate electrode layer of the TFT structure, and the resistance of this gate electrode layer (24) is reduced by subsequent processing. For example, a silicide layer (32) may be formed over the gate electrode layer (24) which has the added advantage of reducing the transparency of the insulated gate structure (22, 24) of the TFT, thereby reducing the dependency of the TFT characteristics on light conditions.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: April 30, 2002
    Assignee: U.S. Philips Corporation
    Inventor: Stephen J. Battersby
  • Patent number: 6380083
    Abstract: A process for fabricating a semiconductor device with copper interconnects is disclosed. In the process of the present invention, a layer of dielectric material is formed on a substrate. A barrier layer to prevent copper diffusion is then deposited over the entire surface of the substrate. A dual copper layer is formed on the barrier layer. The dual layer has a copper layer deposited by PVD and a copper layer deposited by electroplating. The copper layers are adjacent to each other. The ratio of the thickness (X) of the electroplated, layer to the thickness of the PVD layer (Y) is about 1:0.5 to about 1:2. The thickness of the electroplated layer is at least about 3 &mgr;m. The thickness of the PVD copper layer is at least about 100 nm. The thickness of the two layers is selected to effect recrystallization of the electroplated copper from a small grain size (0.1 &mgr;m to 0.2 &mgr;m) to a large grain size (1 &mgr;m or greater).
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: April 30, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Michal Edith Gross
  • Patent number: 6380075
    Abstract: A method for forming an open-bottom liner for a conductor in an electronic structure and devices formed are disclosed. In the method, a pre-processed electronic substrate that has a dielectric layer on top is first provided. Via openings are then formed in a dielectric layer to expose an underlying conductive layer. The electronic substrate is then positioned in a cold-wall, low pressure chemical vapor deposition chamber, while the substrate is heated to a temperature of at least 350° C. A precursor gas is then flowed into the CVD chamber to a partial pressure of not higher than 10 mTorr, and metal is deposited from the precursor gas onto sidewalls of the via openings while bottoms of the via openings are substantially uncovered by the metal. The present invention method may be further enhanced by, optionally, modifications of a I-PVD technique or a seed layer deposition technique.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: April 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Chao-Kun Hu, Sandra Guy Malhotra, Fenton Read McFeely, Stephen Mark Rossnagel, Andrew Herbert Simon
  • Patent number: 6380063
    Abstract: A semiconductor device having borderless contacts thereby providing a device having a reduced overall size. In particular, the device includes a plurality of shallow trench isolations and a plurality of dielectric isolations thereon to separate the adjoining device components and prevent shorts. Sidewall spacers surrounding and extend slightly above the device gates and dielectric isolations to further prevent shorts. A layer of conductive material atop each gate and diffusion region provides for coplanar contact surfaces. A layer of silicide beneath select regions of the conductive layer enhance electrical conductivity within the device. An internal wireless interconnection to electrically connect diffusion regions of different logic devices within the structure is also provided.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: April 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Chediak, Thomas G. Ference, Kurt R. Kimmel, Alain Loiseau, Randy W. Mann, Jed H. Rankin
  • Patent number: 6380016
    Abstract: The specification describes a CMOS compatible technique for programming MOS ROM devices. The technique involves doping the polysilicon gates of selected ROM devices with impurities having a type complementary to the channel, thereby raising the threshold voltage of those selected devices to a value above the operating voltage of the memory array. The programming step can be performed at the same time the CMOS gates are complementary doped thus allowing the ROM array to be programmed without additional processing steps.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: April 30, 2002
    Inventor: Ross Alan Kohler
  • Patent number: 6378109
    Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures of transistor gate oxide. A methodology is provided that is a practical approach to full-chip crosstalk noise verification and gate oxide integrity analysis. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups. Selected signal lines are then fully simulated to determine gate oxide field strengths on transistors connected to the selected signal lines.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Duane J. Young, Franciso A. Cano, Nagaraj N. Savithri