Patents Examined by Charles Bowers
  • Patent number: 6376871
    Abstract: A semiconductor device includes a photodetector having a junction at which a first conductive type first semiconductor portion and a second conductive type second semiconductor portion are joined to each other. In this photodetector, division regions are formed in part of the first semiconductor portion in such a manner as to cross the first semiconductor portion and partially enter the second semiconductor portion, so that the junction is divided into a plurality of parts by the division regions, to form a plurality of photodetector regions having the divided junction parts.
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: April 23, 2002
    Assignee: Sony Corporation
    Inventor: Chihiro Arai
  • Patent number: 6376294
    Abstract: A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: April 23, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Kuo-Chyuan Tzeng, Wen-Chuan Chiang, Wen-Cheng Chen, Chen-Jong Wang
  • Patent number: 6376286
    Abstract: A silicon on insulator (SOI) field effect transistor (FET) structure is formed on a conventional bulk silicon wafer. The structure includes an electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the structure includes isolating the FET active region from other structures in the silicon substrate by forming an insulating trench about the perimeter of the FET and forming an undercut beneath the active region to reduce or eliminate junction capacitance between the source and drain regions and the silicon substrate.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dong-Hyuk Ju
  • Patent number: 6376335
    Abstract: A semiconductor wafer manufacturing process is disclosed wherein extremely flat, double side polished semiconductor wafers having enhanced gettering characteristics on the back surface are produced. The process includes creating an enhanced gettering layer on the back surface of a double side polished semiconductor wafer. A protective layer is subsequently grown on the enhanced gettering layer and the wafer is subsequently subjected to a second double side polishing operation. Finally, the protective layer is removed and the front surface final polished to produce an extremely flat semiconductor wafer having enhanced gettering characteristics on the back surface.
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: April 23, 2002
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: David Zhang, Kanyin Ng, Henry F. Erk
  • Patent number: 6376303
    Abstract: A method of manufacturing a capacitor having a high storage capacitance and a method of fabricating semiconductor devices incorporating the same include measures to ensure that the substrate and/or components of the device are not thermally damaged during the process of forming a sacrificial structure of doped oxide layers used as a form in producing the storage electrode of the capacitor. The oxide layers are formed over the substrate by LPCVD or PECVD, which processes can be carried out at a temperature of only about 400-600° C. Each one of an adjacent pair of the doped oxide layers has a different etching rate from the other as the result of a difference (type or amount) in impurities contained in the oxide layers. At least one hole is formed in the sacrificial structure to create a side wall of the sacrificial structure. The side wall is etched so that repeating tooth-like prominences and depressions are formed at the side wall as the result of the different etching rates of the oxide layers.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: April 23, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Wook Seo, Jeon Sig Lim
  • Patent number: 6376282
    Abstract: A semiconductor device package is formed with a lead frame including a plurality of lead members positioned in an array, and a semiconductor die is secured to the lead frame. At least one pair of bus bars is connected to the lead frame and positioned over the semiconductor die, with the bus bars including a plurality of inner-digitized bond fingers. The inner-digitized bond fingers are formed from a series of alternating projections and recesses on each bus bar. A plurality of bond wires electrically couples the lead members to the semiconductor die. Other bond wires electrically couple the inner-digitized bond fingers of the bus bars to the semiconductor die. The bond wires attached to the inner-digitized bond fingers have a substantially uniform loop height and length, providing for easier manufacture and inspection of the semiconductor device package.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6376262
    Abstract: An optical endpoint system controls the overetching of a semiconductor device by using double optical endpoint detection. With a complex spacer, the system monitors the chemistry change at both the top TEOS/nitride interface and the bottom nitride/TEOS interface. This double optical endpoint method reduces the possibility of overetching the layers regardless of the variations in the thickness of the incoming film or the etching characteristics of the etch chamber.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 23, 2002
    Assignees: National Semiconductor Corporation, Tokyo Electron Limited
    Inventors: Danielle Ki'ilani Kempa, Sandra Hyland
  • Patent number: 6376343
    Abstract: Deleterious roughness of metal silicide/doped Si interfaces arising during conventional salicide processing for forming shallow-depth source and drain junction regions of MOS transistors and/or CMOS devices due to poor compatibility of particular dopants and metal suicides is avoided, or at least substantially reduced, by implanting a first (main) dopant species having relatively good compatibility with the metal silicide, such that the maximum concentration thereof is at a depth above the depth to which silicidation reaction occurs and implanting a second (auxiliary) dopant species having relatively poor compatibility with the metal silicide, wherein the maximum concentration thereof is less than that of the first (main) dopant and is at a depth below the depth to which silicidation reaction occurs. The invention enjoys particular utility in forming NiSi layers on As-doped Si substrates.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew S. Buynoski, Paul R. Besser, Qi Xiang
  • Patent number: 6376354
    Abstract: A wafer-level packaging process comprising: forming a patterned photoresist on a wafer covering a plurality of scribe lines and bump forming locations; forming a stress buffer layer on the regions not covered by the patterned photoresist; after removal of the patterned photoresist a plurality of first openings are defined in the stress buffer layer that also exposes the scribe lines; arranging either a stencil or a second patterned photoresist having a plurality of second openings over the wafer to cover the stress buffer layer and scribe lines, such that the second openings expose the first openings; filling a solder material in the openings; performing a reflow process, wherein according to the use of either the stencil or second photoresist, the reflow is respectively performed after or before the removal thereof. After dicing, the thus-packaged wafer can be directly connected onto an external carrier.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: April 23, 2002
    Assignee: Apack Technologies Inc.
    Inventor: Muh-Min Yih
  • Patent number: 6376387
    Abstract: According to one aspect of the invention, a method of processing a wafer is provided. The wafer is located in a wafer processing chamber of a system for processing a wafer. A silicon layer is then formed on the wafer while the wafer is located in the wafer processing chamber. The wafer is then transferred from the wafer processing chamber to a loadlock chamber of the system. Communication between the processing chamber and the loadlock chamber is closed off. The wafer is then exposed to ozone gas while located in the loadlock chamber, whereafter the wafer is removed from the loadlock chamber out of the system.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: April 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: David K Carlson, Paul B. Comita, Norma B. Riley, Dale R. Du Bois
  • Patent number: 6376373
    Abstract: While conventionally, a Co film is deposited by directional sputtering directly on a source/drain diffusion layer formed on the surface of an Si substrate while the substrate is being heated, a thin oxide film is formed on the source/drain diffusion layer and then, the Co film is deposited by directional sputtering while the substrate is being heated. By doing this, an inner Co—Si layer the composition of which is thermally unstable is formed and a Co—Si—O layer is formed on the Co—Si layer. After the remaining unreacted Co film and the Co—Si—O layer are selectively removed, a high-temperature heat treatment is performed, so that the inner Co—Si layer is transformed into a CoSi2 layer to increase the film thickness. The formation of the oxide film curbs the speed of reaction between Co and Si, so that a Co—Si layer of the same thickness as that in the wide region can be formed in the fine region.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: April 23, 2002
    Assignee: Matsushita Electronics Corporation
    Inventors: Kikuko Nakamura, Tatsuo Sugiyama, Shinichi Ogawa
  • Patent number: 6376329
    Abstract: A projection exposure apparatus for exposing a semiconductor wafer to a pattern, formed on a reticle, using a projection lens system. An alignment optical system is disposed at a backside of the wafer which is remote from the projection lens system. The alignment optical system detects an alignment mark provided on the frontside of the wafer from the backside of the wafer. Thus the wafer alignment mark is detected without being adversely affected by integrated circuit layers, e.g. photoresist, metallization, etc. applied to the principal surface (frontside) of the wafer, and the reticle and wafer can be aligned accurately. Any tilting or wedging of the wafer, i.e. non-normality to the incident light beam, is detected and corrected for.
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: April 23, 2002
    Assignee: Nikon Corporation
    Inventors: Michael R. Sogard, John H. McCoy
  • Patent number: 6376355
    Abstract: A method for forming a metal interconnection filing a contact hole or a groove having a high aspect ratio. An interdielectric layer pattern having a recessed region corresponding to the contact hole or the groove is formed on a semiconductor substrate, and a barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer, thereby exposing the barrier metal layer formed on the sidewalls and the bottom of the recessed region. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: April 23, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mee-young Yoon, Sang-in Lee
  • Patent number: 6376315
    Abstract: A method of manufacturing one or more trench DMOS transistors is provided. In this method, one or more or more body regions adjacent one or more trenches are provided. The one or more trenches are lined with a first insulating layer. A portion of the first insulating layer is removed along at least the upper sidewalls of the trenches, exposing portions of the body regions. An oxide layer is then formed over at least the exposed portions of the body regions, resulting in regions of reduced majority carrier concentration within the body regions adjacent the oxide layer. This modification of the majority carrier concentration in the body regions is advantageous in that a low threshold voltage can be established within the DMOS transistor without resorting to a thinner gate oxide (which would reduce yield and switching speed) and without substantially increasing the likelihood of punch-through.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 23, 2002
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6376264
    Abstract: A method and apparatus for monitoring and evaluating effects of electrostatic discharge associated with semiconductor manufacturing are disclosed. The method may include, for example, exposing a test photomask that contains an ESD sensitive geometry to a single or a variety of semiconductor manufacturing procedures. The test photomask may be analyzed to determine how much, if any, degradation of its geometry has occurred as a result of the exposure.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: April 23, 2002
    Assignee: DuPont Photomasks, Inc.
    Inventor: Andreas Englisch
  • Patent number: 6376304
    Abstract: A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 23, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hideyuki Matsuoka, Shinichiro Kimura, Toshiaki Yamanaka
  • Patent number: 6376261
    Abstract: A method is provided for manufacturing, the method including processing a first workpiece in a nitride processing step and measuring a thickness of a field oxide feature formed on the first workpiece. The method also includes forming an output signal corresponding to the thickness of the field oxide feature. In addition, the method includes feeding back a control signal based on the output signal to adjust processing performed on a second workpiece in the nitride processing step to adjust a thickness of a field oxide feature formed on the second workpiece toward at least a predetermined threshold value.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices Inc.
    Inventor: William Jarrett Campbell
  • Patent number: 6376340
    Abstract: Polycrystalline silicon film forming methods to improve movement of electrons and holes and thus allow the fabrication of high performance semiconductor elements is needed. In a method of the present invention, polycrystalline is formed utilizing as a material, a chemical compound comprising at least one type of impurity from among tin (Sn), germanium (Ge) and lead (Pb) and a polycrystalline silicon film doped with impurities from at least one type from among tin (Sn), germanium (Ge) and lead (Pb) thus formed. In another method, polycrystalline silicon is formed, and the polycrystalline silicon film thus obtained is afterwards then doped with an impurity consisting of at least one type from among tin (Sn), germanium (Ge) and lead (Pb).
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: April 23, 2002
    Assignee: Sony Corporation
    Inventors: Yuuichi Sato, Hisayoshi Yamoto, Hideo Yamanaka, Hajime Yagi
  • Patent number: 6376268
    Abstract: An optoelectronic assembly having an insulating substrate with a planar surface and a metal layer bonded to the planar surface such that selected regions of the substrate are exposed and a step is produced between the substrate and a top surface of the metal layer. An active optical device is mounted on the metal layer and a passive optical device is aligned with the active device using the step as a fiduciary for positioning the former. The metal layer provides an electrical path to the active device. The thickness of the metal layer is selected such that the heat generated by the active device is dissipated, the substrate does not interfere with the propagation of light along the first optical axis, and such that the in-plane coefficient of thermal expansion (CTE) of the metal layer is constrained by the substrate. The optoelectronic assembly is also suitable for mounting active devices provided with submounts or without.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: April 23, 2002
    Assignee: Intel Corporation
    Inventor: Jean-Marc Verdiell
  • Patent number: 6376278
    Abstract: A first adhesive tape is attached to a first major surface of a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor chip regions. Protrusion electrodes are formed on a second major surface of the semiconductor wafer within the plurality of semiconductor chip regions. Portions of the semiconductor wafer located between the plurality of chip regions are removed to form a plurality of semiconductor chips. Intervals between the semiconductor chips are then expanded. Respective first major surfaces of the wiring substrates are coupled to the corresponding second major surfaces of the semiconductor chips by the protrusion electrodes to form preliminarily structures each of which is comprised of the semiconductor chip and the wiring substrate. A second adhesive tape is attached to second major surfaces of the wiring substrates. The first adhesive tape is removed from the semiconductor chips.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: April 23, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshimi Egawa, Kazumi Shinchi, Takeshi Niigaki