Patents Examined by Charles Bowers
  • Patent number: 6376333
    Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming a first insulating film on a first substrate; forming a second insulating film on the first insulating film; forming an amorphous silicon film on the second insulating film; holding a metal element that promotes the crystallization of silicon in contact with a surface of the amorphous silicon film; crystallizing the amorphous silicon film through a heat treatment to obtain a crystalline silicon film; forming a thin-film transistor using the crystalline silicon film; forming a sealing layer that seals the thin-film transistor; bonding a second substrate having a translucent property to the sealing layer; and removing the first insulating film to peel off the first substrate.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: April 23, 2002
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai, Satoshi Teramoto
  • Patent number: 6376350
    Abstract: The present invention is directed to a method of forming a semiconductor device. In one illustrative embodiment, the method comprises forming a layer of polysilicon and forming a recess in the layer of polysilicon. The method further comprises forming a metal region in the recess and patterning the layer of polysilicon to define a gate stack comprised of the metal region and the layer of polysilicon.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: April 23, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael P. Duane, Jeffrey C. Haines, Frederick N. Hause
  • Patent number: 6376331
    Abstract: A semiconductor device is herein disclosed which comprises a plurality of element regions formed on a first conductive type semiconductor substrate, element isolation regions for isolating the element regions from each other, and gate electrodes on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: April 23, 2002
    Assignee: NEC Corporation
    Inventor: Minoru Higuchi
  • Patent number: 6376328
    Abstract: A silicon layer containing microcrystal is formed on a semiconductor substrate 10 having an amorphous silicon layer 61a formed on the surface thereof (t1 and t2). Continuously, HSGs (hemispherical grains) are formed, in the same furnace, on the silicon layer 61a using microcrystal on the silicon layer 61a as a nucleus (t2 and t3). Further, a source gas containing impurities is introduced into the furnace to diffuse impurities into the HSGs (t3 and t4), wherein a lower electrode is formed. Also, during the processes from t1 through t4, the partial pressure of water and oxygen in the furnace is set to 1×10−6 Torr or less. Furthermore, during the processes from t1 through t4, the temperature in the furnace is set to 550 through 600° C.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: April 23, 2002
    Assignee: NEC Corporation
    Inventors: Fumiki Aiso, Toshiyuki Hirota
  • Patent number: 6376381
    Abstract: Microelectronic substrate assemblies are planarized using methods, planarizing solutions and planarizing machines according to various embodiments of the present invention. A substrate is assembly pressed against a planarizing surface of a fixed-abrasive polishing pad, covering an operative portion of the planarizing surface with a non-abrasive planarizing solution, and moving the substrate assembly and/or the polishing pad with respect to the other. The fixed-abrasive polishing pad includes a body having a suspension medium and abrasive particles fixedly attached to the suspension medium at the planarizing surface. The substrate assembly is a stop-on-feature device including a substrate, a polish-stop layer formed over the substrate to conform to a topography of features on the substrate, and a cover layer formed over the polish-stop layer.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: April 23, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Gundu M. Sabde
  • Patent number: 6376367
    Abstract: A semiconductor device having good electrical properties, and a method of manufacturing this semiconductor device by forming an insulation layer on a first wiring layer and then, in this insulation layer, simultaneously forming a second wiring layer and a contact layer for connecting the first wiring layer and the second wiring layer. A first mask having an opening over a wiring trench in which the second wiring layer will be formed is formed on the insulation layer. A second mask having an opening for a through-hole where the contact layer is to be formed is then formed over the insulation layer and first mask. The insulation layer is then etched using the second mask as a mask. Then the insulation layer is again etched using the first mask as a mask to form wiring trench and through-hole. The wiring trench and through-hole are then filled with a conductive material to form the second wiring layer and contact layer.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: April 23, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Hiroshi Okamura
  • Patent number: 6376365
    Abstract: A method for fabricating semiconductor devices having multi-layered wiring structure with an advanced reliability and free from shortcircuit failure between the upper and lower wirings is provided. The method has a step for forming on a first insulating film, having a conductive body exposed thereon, a second insulating film so as to cover the conductive body, and a step for forming by etching a recess to the second insulating film so as to reach the conductive body. In this case at least the lower portion of the second insulating film is formed with a material showing a faster etching rate over at least the upper portion of the first insulating film.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: April 23, 2002
    Assignee: Sony Corporation
    Inventor: Atsushi Tsuji
  • Patent number: 6376279
    Abstract: A semiconductor package manufacturing method includes: providing a rerouting film; attaching a semiconductor wafer having integrated circuits to the rerouting film, such that chip pads of the integrated circuits correspond to via holes of the rerouting film; forming a solder filling in each of the via holes to electrically connect the chip pads to the metal pattern layer; forming external terminals on terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual semiconductor packages. A method further includes forming a protection layer on the solder filling. Instead of the semiconductor wafer, individual integrated circuit chips can be attached on the rerouting film.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: April 23, 2002
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Yong Hwan Kwon, Sa Yoon Kang, Nam Seog Kim, Dong Hyeon Jang
  • Patent number: 6376352
    Abstract: A method of forming a membrane for use in conjunction with a semiconductor carrier and the membrane which includes an electrically insulating substrate and an interconnect pattern formed on the substrate. A stud is coupled to the interconnect pattern over the substrate by forming a gold ball, preferably by gold ball bonding techniques, and coating a portion of the gold ball with a compliant material, preferably an epoxy resin. The coating is filled with a material having sufficient hardness to be capable of penetrating the oxide film on the contact pads of semiconductor devices. The flakes are preferably silver or silver-based.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: April 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Richard W. Arnold, Weldon Beardain, Lester L. Wilson, James A. Forster
  • Patent number: 6372605
    Abstract: During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: April 16, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Stephen C. Kuehne, Alvaro Maury, Scott F. Shive
  • Patent number: 6372639
    Abstract: A workpiece and method are provided for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device. The workpiece includes an active area and N potential contact openings covered with a dielectric layer, a first through hole etched in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, a monolithic polysilicon plug deposited in the first through hole, and N−1 second through holes etched in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2. According to one aspect of the invention, the workpiece includes N−1 conductors traversing the active area, the N contact openings are disposed adjacent to the N−1 conductors, and each of the N contact openings is separated from the other contact openings by one of the N−1 conductors.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: April 16, 2002
    Assignee: Micron Technology, Inc.
    Inventor: William Stanton
  • Patent number: 6372668
    Abstract: The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sey-Ping Sun, Homi Nariman, Hartmut Ruelke
  • Patent number: 6372640
    Abstract: The present invention mainly provides a method to locally form metal silicide on an integral circuit and to avoid the phenomenon of leakage current which is caused by metal silicide formed between the memory cells on the same word line. The method of the present invention achieves the above objectives by principally using a design rule to adequately arrange elements within a proper distance. In an embodiment, in order to form metal silicide layers on an integral circuit and to avoid metal silicide formed between two neighboring memory cell on the same word line, a dielectric layer is first formed in the spaced region between the two neighboring memory cells to be used as a mask. Thus, in a following selective etching process, a part of the silicon substrate within the above spaced region can be protected and not exposed. Therefore, no metal silicide is formed in the spaced region, and the above objective is achieved.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: April 16, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Ying-Tso Chen, Erh-Kun Lai, Hsin-Huei Chen, Shou-Wei Hwang, Yu-Ping Huang
  • Patent number: 6372635
    Abstract: An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, Lynne A. Okada, Ramkumar Subramanian, Calvin T. Gabriel
  • Patent number: 6372003
    Abstract: According to the present invention, a process is provided for producing crystalline ceric oxide particles having a particle diameter of 0.005 to 5 &mgr;m, which comprises the steps of reacting a cerium (III) salt with an alkaline substance in an (OH)/(Ce3+) molar ratio of 3 to 30 in an aqueous medium in an inert gas atmosphere to produce a suspension of cerium (III) hydroxide, and blowing oxygen or a gas containing oxygen into the suspension at a temperature of 10 to 95° C. and at an atmospheric pressure.
    Type: Grant
    Filed: July 9, 1999
    Date of Patent: April 16, 2002
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Toshio Kasai, Isao Ota, Takao Kaga, Tohru Nishimura, Kenji Tanimoto
  • Patent number: 6372638
    Abstract: A method for forming void free tungsten plug contacts (56a-56c) begins by etching a contact opening (55a-55c) using a C2F6 and CHF3 chemistry. The etch chemistry is then changed to an O2 and CH3F chemistry in order to insitu remove the contact photoresist while tapering an upper portion of the contact opening. A tungsten deposition process is then performed whereby the tapered portion of the contact reduces the effects of nonconformal and step-coverage-inconsistent tungsten deposition wherein voids in the contact are either substantially reduced or totally avoided within the contact structure. The reduction of or total elimination of voids (22) within the tungsten contact will increase yield, increase reliability, and reduce electromigration failures within integrated circuit devices.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: April 16, 2002
    Assignee: Motorola, Inc.
    Inventors: Robert Arthur Rodriguez, Heather Marie Klesat
  • Patent number: 6372606
    Abstract: A method of forming an isolation trench in a semiconductor substrate includes the steps of sequentially depositing first and second insulating layers over the substrate, subsequently etching the second and first insulating layers to define active and non-active regions according to a patterned masking photoresist layer, excessively etching a part of the thickness of the substrate, removing parts of the first insulating layer by undercutting the sides of the non-active region so as to expose parts of the substrate in the active region, etching the substrate by using the second insulating layer as a trench patterned masking layer to form a trench in which the edges of the exposed parts of the substrate are rounded, depositing a third insulating layer on the bottom and side walls of the trench and the rounded parts of the substrate to repair the parts of the substrate damaged when forming the trench, depositing a fourth insulating layer over the second insulating layer so as to completely fill the trench, etchin
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: April 16, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-Chul Oh
  • Patent number: 6371135
    Abstract: A method is described for removing a particle from a surface of a semiconductor wafer. In general, the method involves positioning an electrically conductive surface near the particle to be removed. An electrical charge is created on the electrically conductive surface. A charged particle beam is formed, wherein the charged particle beam includes particles having an electrical charge opposite the electrical charge of the electrically conductive surface. The charged particle beam is directed at the particle to be removed. When struck by the charged particle beam, the particle to be removed absorbs a portion of the charged particles of the charged particle beam and acquires an electrical charge opposite the electrical charge of the electrically conductive surface.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthew S. Ryskoski
  • Patent number: 6372673
    Abstract: Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Paul R. Besser, Minh Van Ngo, Christy Mei-Chu Woo, George Jonathan Kluth
  • Patent number: 6372604
    Abstract: There is provided a method for forming a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than the CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Maiko Sakai, Takashi Kuroi, Katsuyuki Horita