Abstract: The present invention relates to a memory structure and a method for forming the same. The memory structure includes a first substrate and an isolation structure. The first substrate includes a substrate layer and a storage layer. The substrate layer has a first surface and a second surface opposite to the first surface. The storage layer is disposed on the first surface of the substrate layer. The substrate layer has a doped well. The isolation structure penetrates through the substrate layer and is disposed at an edge of the doped well for isolating the doped well and the peripheral substrate layer. The memory structure can avoid current leakage between the doped well and the substrate layer so as to improve the performance.

Abstract: Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

Abstract: The present application provides a method for fabricating a thin film transistor, a method for fabricating an array substrate, and a display apparatus. A method for fabricating a thin film transistor including: providing a substrate; covering an isolating layer on the substrate; coating an active layer precursor solution on the isolation layer; forming an active layer thin film by the active layer precursor solution; dividing the active layer thin film into a small module active layer, the mobility of the active layer of the thin film transistor is increased, and to drive the quantum dot light emitting device of the array substrate through the thin film transistor with high mobility to improve the display luminescence performance of the display apparatus.

Abstract: The present disclosure provides a photosensitive device. The photosensitive device includes a donor-intermix-acceptor (PIN) structure. The PIN structure includes an organic hole transport layer; an organic electron transport layer; and an intermix layer sandwiched between the hole transport organic material layer and the electron transport organic material layer. The intermix layer includes a mixture of an n-type organic material and a p-type organic material.

Abstract: A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.

Abstract: Methods for forming bonded assemblies using metal inverse opal and cap structures are disclosed. In one embodiment, a method for forming a bonded assembly includes positioning a substrate against a polymer support that is porous, depositing a metal onto and within the polymer support, disposing a cap layer to the polymer support opposite of the substrate to form a bottom electrode, and removing the polymer support from between the substrate and the cap layer to form a metal inverse opal structure disposed therebetween.

Abstract: Provided is a nanosheet semiconductor device. In embodiments of the invention, the nanosheet semiconductor device includes a channel nanosheet formed over a substrate. The nanosheet semiconductor device includes a buffer layer formed between the substrate and the channel nanosheet. The buffer layer has a lower conductivity than the channel nanosheet.

Abstract: Memory devices and methods of forming the same include forming a memory stack over a bottom electrode. The memory stack has a free magnetic layer formed on the tunnel barrier layer. A first boron-segregating layer is formed directly on the free magnetic layer. An anneal is performed to cause boron to leave the free magnetic layer at an interface with the first boron-segregating layer. A top electrode is formed over the memory stack.

Abstract: A light-emitting device with high luminance which has high uniformity in color and intensity can be provided. The light-emitting device includes a mounting substrate, a plurality of light-emitting elements disposed on the mounting substrate side by side, a wavelength conversion plate provided over the plurality of light-emitting elements and having a side surface, and a plurality of bumps disposed on the mounting substrate to abut against the side surface of the wavelength conversion plate, so as to determine a position of the wavelength conversion plate.

Abstract: A wafer level package with at least one integrated antenna element includes a chip layer with at least one chip, a dielectric layer as well as an antenna layer arranged between the chip layer and the dielectric layer.

Abstract: Methods and apparatuses for performing cycles of aspect ratio dependent deposition and aspect ratio independent etching on lithographically patterned substrates are described herein. Methods are suitable for reducing variation of feature depths and/or aspect ratios between features formed and partially formed by lithography, some partially formed features being partially formed due to stochastic effects. Methods and apparatuses are suitable for processing a substrate having a photoresist after extreme ultraviolet lithography. Some methods involve cycles of deposition by plasma enhanced chemical vapor deposition and directional etching by atomic layer etching.

Abstract: The present invention provides a process of fabricating a capacitive microphone such as a MEMS microphone. In the process, one electrically conductive layer is deposited on a removable layer, and then divided or cut into two divided layers, both of which remain in contact with the removable layer as they were. One of the two divided layers will become or include a movable or deflectable membrane/diaphragm that moves in a lateral manner relative to another layer, instead of moving toward/from another layer. A motional sensor is optionally fabricated within the microphone to estimate the noise introduced from acceleration or vibration of the microphone for the purpose of compensating the microphone output through a signal subtraction operation.

Abstract: A microelectromechanical component including, vertically at a distance from one another, a substrate device, a first, a second, and a third functional layer, a vertical stop being formed between the second and third functional layer, the vertical stop having a stop area on a surface of the second functional layer facing the third functional layer, wherein the second functional layer is connected to the first functional layer in a connecting area allocated to the stop area.

Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Abstract: A manufacturing process of an element chip, comprising a substrate preparing step for preparing a substrate having first and second sides opposed to each other, and including a plurality of dicing regions and element regions defined by the dicing regions, the first side being covered by a protective film, a first laser-grooving step for forming a plurality of grooves by irradiating a laser beam to the first side along the dicing regions, and a plasma-dicing step for plasma-etching the substrate along the grooves in depth through a plasma exposure, thereby to dice the substrate into a plurality of element chips, wherein the second side of the substrate and an annular frame are held on a holding sheet in the substrate preparing step, and wherein the laser beam is irradiated only in a region inside an outer edge of the substrate in the first laser-grooving step.

Abstract: The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer.

Abstract: Provided are an array substrate, a chip on film, a display panel and a display device. The array substrate has a display area and a bonding area located in a periphery of the display area. The array substrate includes a plurality of first bonding pads located in the bonding area, and length directions of the first bonding pads face the display area.

Abstract: A wafer having a device area on one side with a plurality of devices partitioned by division lines is divided into dies. An adhesive tape for protecting devices is attached to the one side of the wafer, the adhesive tape adhering to at least some, optionally all, of the devices. A carrier for supporting the tape is attached to the side of the tape opposite to the one side by an attachment means provided over an entire surface area of the adhesive tape which is in contact with the carrier. The wafer is cut along the division lines. The side of the wafer opposite to the one side is mechanically partially cut, and a remaining part of the cuts in the wafer is mechanically cut and/or cut by laser and/or cut by plasma from the side of the wafer opposite to the one side.

Abstract: Example photoconductive devices and example methods for using photoconductive devices are described. An example method may include providing a photoconductive device having a metal-semiconductor-metal structure. The method may also include controlling, based on a first input state, illumination of the photoconductive device by a first optical beam during a time period, and controlling, based on a second input state, illumination of the photoconductive device by a second optical beam during the time period. Further, the method may include detecting an amount of current produced by the photoconductive device during the time period, and based on the detected amount of current, providing an output indicative of the first input state and the second input state. The example devices can be used individually as discrete components or in integrated circuits for memory or logic applications.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.