Abstract: This flash analog-to-digital converter (ADC) offers the fastest possible high resolution conversion as the quantization level of the input signal is determined in a straightforward structure, whereby no feedback exists. For instance, a 16-bit flash ADC employs approximately 555 rather than 65,535 comparators normally required. In another embodiment only approximately 150 comparators are required. One or two noninverting amplifiers are used.In the preferred embodiment, the ADC input signal is applied to a resistor network coupled between the ADC input and a reference current source. A plurality of comparators is coupled to the resistor network for comparing comparison signals deriving therefrom against ground, and producing a first code. In response thereto, a multiplexer selects one of the comparison signals which is amplified and then converted in an ADC unit into a second code.

Abstract: A digital-to-analog conversion system including: a code conversion circuit for converting an input binary code to a three states code; the code conversion circuit designating each digit from one digit lower than a most significant digit to a least significant digit; when a designated digit and both lower and upper digits thereof are the same, a corresponding digit of the three states code is set to a first state, except for the above case, the designated digit is inverted, and when the upper digit of the designated digit is "0", the corresponding digit of the three states code is set to a second state, and when the digit lower than said designated digit is "1", the corresponding digit of the three states code is set to a third state, and a digital-to-analog conversion means connected to the code conversion and controlled by the three states code for outputting an analog value.

Abstract: In an AD converting device in which an analog random noise is added by analog adding means to an analog signal to be converted and the added output is converted by an AD converter to a digital signal, an analog offset voltage, whose level variation is around (1 to 7) times the quantization step size .DELTA. of the AD converter, is generated by offset generating means and is also applied to the analog adding means. A random noise waveform is stored in a memory, the read-out output of which is converted by DA converting means to an analog random noise having an amplitude about (1/2 to 6).DELTA., and the converted output is used as the above-said random noise. A digital value of the offset voltage and the digital noise waveform are subtracted from the output of the AD converter, as required.

Abstract: A systematic method and apparatus for constructing a run length limited code in which the minimum number of continuous bits of the same binary value is constrained to d and the maximum number thereof is constrained to k.In converting m-bit data words to n-bit code words (n>m) to construct the run length limited code, selection means for n-bit code words usable to meet the d, k-constraint and a concatenation rule of the code words selected by the selection means are introduced.The selection means divides each of 2.sup.n n-bit bit sequences into a leading block L having l continuous bits of the same binary value, an end block R having .gamma. continuous bits of the same binary value and an intermediate block B having b(=n-l-.gamma.) bits between the blocks L and R.Only those n-bit bit sequences in which the blocks B thereof completely meet the d, k-constraint and the blocks L and R thereof meet conditions uniquely defined for given d and k are used as the code words.

Abstract: In an electronic conversion circuit for converting an analog value to digital codes or digital codes to an analog value, the circuit comprises at least two conversion hold blocks. Each of the analog processing units has two functions, that is, one function is to perform sampling of the analog value and to circularly convert the analog value to an output analog value in order to obtain a digital value based on the output analog value, and the other function is to sequentially input digital codes and to convert digital codes in order to obtain the analog value.

Abstract: Disclosed is a decompaction system for reading compacted paralled data from a memory and providing in real time uncompacted serial data therefrom. The decompaction system is especially suited to be utilized in pin electronics automatic test equipment for real time testing of units such as integrated circuits, circuit boards, etc. The decompaction system includes a separate channel for each pin of the unit under test (UUT) and is capable of decoding a number of types of compacted parallel data and providing serail data to each pin of the UUT in the most prevalently used test patterns. The data is compacted by software algorithms according to these patterns, stored in a memory and retrieved and decoded by the decompaction system during real-time testing of the UUT. In a specific embodiment, compacted parallel data is stored in 16-bit words in a separate memory for each channel, and is decompacted into serial data sequences of from 8 to 4096 bits per channel for each access of the respective memory.

Abstract: A semiconductor circuit is provided with a constant current circuit, a resistor network to which a current from the constant current circuit is supplied, and a device between the constant current circuit and the resistor network for switching the current supplied from the constant current circuit to the resistor network.

Abstract: The present invention relates to a digital-to-digital code converter, or decimator, which implements sinc.sup.3 processing. The input signal (X) to the code converter comprises a series of groups, each group including a series of N digital sample values occurring at high rate (1/.tau.) which are converted within the converter, using sinc.sup.3 processing, into a single digital value occurring at, for example, a (1/N).tau. rate for delivery to the converter output (Y). The code converter comprises three processing stages in cascade, where each stage includes separate accumulation means, each accumulation means arranged to add, during each series of N input sample values, the signal value received by that stage from the next preceding stage.

Abstract: A device for converting time varying signals which represent sin .theta. and cos .theta. of an angle .theta., where can take on values over a range, to an n bit digital signal. The range is typically 2.pi. radians and is segmented into 2.sup.n+1 -4 segments. The segments are mapped into 2.sup.n -1 amplitudes, and are encoded as the n bit digital signal. The invention is particularly useful as an angle digitizer where .theta. represents the phase difference between an input signal and a reference signal. As an angle digitizer, harmonic rejection is enhanced by the efficient use of the n bits to distinguish amplitude states as opposed to distinguishing merely phase states.

Abstract: An analog-digital converter designed to provide digital data by converting analog input voltage signals into pulse signals by a voltage-frequency converter, and counting said pulse signals by a counter, the improvement being that the A-D converter comprises a sequence controller which selectively supplies low-level or high-level input voltage signals to the A-D converter before analog input signals being measured are received therein.

Abstract: In an integrated circuit for transcoder, a substractor generates a signal representing a difference between an input speech signal and a prediction signal. This signal is transferred to a quantizing unit. The unit quantizes an output signal from the subtractor, and generates a predictive encoded signal. An inverse quantizing unit generates a difference signal. A predictor filter generates the prediction signal to be supplied to the subtractor. A signal path changing unit made up of electronic switches respondes to a mode select signal to suitably change an electric connection among the subtractor, the quantizing unit and the reverse quantizing unit, whereby the integrated circuit device can function as and ADPCM encoder or an ADPCM decoder.

Abstract: The present invention provides a DA converter of the type wherein a group of switch circuits are controlled in response to input digital signals and a plurality of constant current sources are driven in response to on and off of the switch circuits to convert the input digital signals into analogue signals, the DA converter comprising a plurality of lineages of digital input circuits for controlling the switch circuits, whereby digital signals inputted to the input circuits are changed over in order for each lineage to DA convert them.

Abstract: A cogeneration system including a heat engine driving an electrical generator coupled to electrical lines at a site serviced by a utility is disclosed. The system includes supervisory means for monitoring the electrical energy and/or power supplied by the generator, supplied to the site by the utility, and consumed by site electrical loads, for storing monitored electrical data, and for controlling operation of the engine and generator in response to the monitored data. The system further is provided with data representing the energy and power rate structure of the local utility, and with a real time clock, and stores monitored electrical data and controls operation of the system in accordance with whether the time corresponds to a utility peak, intermediate, or off-peak energy rate period or to a peak demand measuring period. The system further comprises means for monitoring the thermal energy transferred from the engine to a site thermal load by heat exchange means.

Abstract: A method and apparatus well suited for digitizing an audio signal with as wide a dynamic range as possible. An analog dither signal is added to an analog audio or like data signal to provide an analog data/dither signal. This analog data/dither signal and the analog dither signal are both converted into a digital data/dither signal and a digital dither signal respectively, and the digital dither signal is subsequently subtracted from the digital data/dither signal to obtain a digital data signal equivalent to the analog data signal. The magnitude of the incoming analog data signal may be so high that when the analog dither signal is added thereto, the magnitude of the resulting data/dither signal may exceed the capacity of the analog to digital converter in use. In that case the analog dither signal is either gated off or reduced in magnitude, with the result that the analog to digital converter inputs either the data signal only or the data/dither signal having a magnitude not exceeding its capacity.

Abstract: In compact card-like equipment having an IC chip and a power source cell, an equipment case has a multilayered structure of a pair of upper and lower sheets and a pair of upper and lower panels laminated on a frame, respectively. A flexible substrate and a paper-like cell as a primary cell are provided in the equipment case. The paper-like cell has a pair of positive and negative electrode sheets and a power generating unit interposed therebetween. A sealing member seals the peripheries of the electrode sheets of the paper-like cell. The paper-like cell is received in a receptacle space formed in the frame. The flexible substrate is received in another receptacle space formed in the frame. The electrode sheets of the paper-like cell are electrically connected to terminals of the flexible substrate by means of a film-like connecting member. This compact card-like electronic equipment such as a calculator is thin and compact in size.

Abstract: An arrangement for compensating for non-linear distortion in an input signal to be digitized, comprising an analogue-to-digital converter (2) for converting the input signal into an amplitude-time discrete output signal, means (3) for deriving a set of coefficients which are associated with an orthogonal signal representation of a signal related to the input signal, a memory (4) in which a Table with correction values is stored, means for addressing the memory for reading a correction value from the Table, each of the coefficients determining an address for the memory, means (5) for adding together the correction value and the analogue-to-digital converter output signal for providing a linearized signal, and an adaptive control loop (7,8,16,18) for substituting in the Table the new correction value for the correction value read.

Abstract: An integration type D/A and A/D converter having improved linearity and low power consumption. Logic circuits such as ECL counters consuming a major part of power of the D/A and A/D converters are realized through CMOS process. Current source circuits, current switch circuit and comparator circuit of the integration type A/D converter are realized in IC through bipolar process ensuring high accuracy and low noise. Logic parts such as counter is realized through CMOS process.

Abstract: A digital to analog converter for converting an N-bit digital word into its analog representation including means for splitting the N bits into n sections of N/n bits each. For instance a 12-bit word is split into an odd section and an even section which are processed independently and in parallel. This results in two partial results, V.sub.i and V.sub.p, respectively, representative of the odd and even bit sections. The last step of the conversion is the action of the two partial results V.sub.i and V.sub.p to provide the analog representation of the 12-bit word. Few operators are required to process each section because each bit is converted sequentially. This provides a low cost, compact and simple converter, moreover, since few operators are required, it may be advantageous to use high precision operators as disclosed.

Abstract: In a serial-parallel A/D converter, at least two sets of comparators are provided for the conversion of the low-order bits and are operated in a cyclic fashion. Since the subsequent input can be subjected to the A/D conversion without waiting for the determination of the low-order bits, the conversion speed is increased.

Abstract: A cyclic type D/A converter having an error detection and correction system including: a code conversion circuit for converting a binary code to a multi-states code; a digital-to-analog conversion circuit connected to the code conversion circuit for converting the multi-states code to an analog value; a detection circuit operatively connected to the digital-to-analog conversion circuit for converting the analog value to a digital code; and a control circuit operatively connected to the code conversion circuit, digital-to-analog conversion circuit and detection circuit for calculating a voltage difference between the analog value at a predetermined code value and another analog value adjacent to the predetermined code value, and for calculating a differential non-linearity error from the voltage difference based on the digital code, in order to obtain error and correction values of capacitors forming the digital-to-analog conversion circuit.