Abstract: A test signal output circuit comprising a decoder for decoding test-mode signals from test-mode signal input terminals, and selectors each for, in response to the output of this decoder, selecting specified ones of internal signals of the LSI, and outputting them at the test signal output terminals.In virtue of this, tests of the LSI in operation can be performed substantially without increasing the number of external connection terminals of LSI.

Abstract: Method and apparatus are disclosed for providing an indication relating to certain faults that can occur during data storing operations in an array storage system. In connection with providing the indication, a code byte having a number of code bits is appended to data that is stored on storage devices of the array storage system. When such a fault occurs, predetermined code bits are set to indicate the data operation that was taking place when the fault occurred. In a preferred embodiment, there are two data storing related operations for which predetermined code bits are set when a fault occurs, namely, a data reconstruction operation and a data reassignment operation. Since these operations are typically initiated automatically and are transparent to any host system connected to the array storage system, such a fault indication enables the user to determine the identity of the data storing related operation that was in progress when the fault occurred.

Abstract: Two related methods and apparatus for determining a binary constant to be output from embedded memory arrays into system logic of an integrated circuit when the system logic is being tested, that maximizes improvement to fault coverage of the system logic, are disclosed. The present invention has particular application to digital system testing. The fault coverage of the system logic is improved due to its controllability and observability are indirectly enhanced by the enhanced controllability of the embedded memory arrays. The first related method and apparatus determines the binary constant based on a testability measure selected for the system logic. The second related method and apparatus determines the binary constant based on results from automated test patterns generation for the integrated circuit.

Abstract: A process for generating a vector for testing a digital circuit for a given fault first creates a composite circuit including a fault-present version of the circuit and a fault-free version. An implication graph is developed for the composite circuit and its energy function is derived as a combination of binary and ternary terms. All signal states that are consistent with the circuit function minimize the energy function to zero value. The transitive closure is computed for the binary terms, and redundancies, contradictions, fixations, identification and exclusions are identified. By iteration of implication graphs and transitive closures together with arbitrarily assigned signal values all ternary terms of the energy function are converted to binary terms, after which transitive closure recomputes a set of literals that can be used to generate the desired test vector by a standard branch and bound procedure.

Abstract: A testing apparatus for testing connectivity to a circuit board of an integrated circuit chip disposed on the circuit board. The circuit board has signal transmission circuitry. The integrated circuit chip has pins coupled to the signal transmission circuitry. The pins are for receiving digital signals asserted external to the chip. Each digital signal has a binary value depending upon whether the signal is asserted or not. The testing apparatus tests connectivity of the pins. The testing apparatus has signal assertion and reception circuitry that is coupled to the signal transmission circuitry of the circuit board but is not disposed on the chip. Command sensing, pin state storage, general storage, algorithm execution and general data output circuitry are all disposed on the chip to be tested. The command sensing circuitry is for sensing external assertion of a test command by the signal assertion and reception circuitry. The test command causes the chip to enter a test mode.

Abstract: The present invention relates to a method of displaying an execution status and an execution history of a program for a computer system, associated with a source program and a module relation diagram. The method of displaying program execution according to the present invention displays the processing results of each of execution units, execution statuses of an iteration, a conditional branch, a recursive call and so on super-imposed on the source program displayed on a screen in the vicinity of the respective execution units. Information on execution status is also displayed corresponding to the module relation diagram. Further, a program execution history is preserved so as to allow a reproduced display thereof in the above-mentioned form by request.

Abstract: Debugging of computer programs is necessary for the development of the programs as well as for maintaining the operation of the programs. Symbolic debugging requires the ability to relate the current position in the object code program to the corresponding position in the source code. In the absence of compiler optimization, correlating the source and object code elements is a straightforward procedure. However, when the object code has been optimized, the relation between the source code constructs and object code instructions can become convoluted and complex. A correlation technique for optimized code is disclosed which maps the source constructs (source units) through each of the optimization operations by use of compilation nodes and associated source units to build a table which relates ranges of object instructions to the source units which produced the object instructions.

Abstract: An error correction apparatus for reproducing data that have been multi-encoded with error correcting codes and recorded on a recording medium, and for correcting errors contained in the reproduced data through decoding the same. The apparatus includes: a reproducing circuit for reproducing the data encoded and recorded on the recording medium; a memory for storing the reproduced data; an error correction circuit adapted to correct errors of the data with the error correcting codes from the lowest to the highest levels in due order, for detecting that correction is impossible at the highest level and at an intermediate level between the lowest and the highest levels and for outputting a first and a second correction incapability detecting signals, respectively; and a controller responsive to the first and second correction incapability detecting signals for controlling the reproduction circuit, the memory and the error correction circuit.

Abstract: An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit.

Abstract: A method is described for verifying the operation of next state logic within a write state machine for automatically programming and erasing a flash memory. Verification of the next state logic's operation begins by configuring the write state machine in a test mode. Afterward, the next state logic is cycled through its possible output states by providing the next state logic with all possible input states. Outputs from next state logic are compared to expected outputs, thereby verifying the operation of the next state logic. Also described is circuitry for verifying the operation of next state logic within a write state machine. The circuitry includes test registers for storing test signals. In response to the test signals a first means isolates the next state logic from the write state machine. A second means provides alternative inputs to the next state logic in response to the test signals.

Abstract: In a system which performs an inference based on fault tree knowledge, a guidance and a formula of definition can be displayed in a window on a CRT display screen by selecting the individual items from a fault tree on the display screen by using, for example, a soft key. For displaying an abnormal course in one display screen, only events relevant to the abnormal course is picked up, and the fault tree is then reedited, so that the reedited fault tree can be automatically displayed on the display screen.

Abstract: A memory module, parity bit emulator, and method which emulate storing and retrieving a parity bit from memory. The memory module includes a memory for storing a data word which is retrieved from the memory during the read cycle. The memory module also includes a parity bit emulator which includes a parity bit generator. The parity bit generator is responsive to the retrieved data word and generates in response a corresponding parity bit during the read cycle. The memory module also includes an input/output port for outputting the retrieved data word and the generated parity bit during the read cycle.

Abstract: An apparatus for analyzing faults in a memory having a redundancy circuit, includes an algorithmic pattern generator which generates address signals to select a memory cell of a memory under test and data which is written to a selected memory cell, a comparison circuit for performing a read operation after data has been written to a selected memory cell by address signals and comparing the data read and the data from the algorithmic pattern generator to determine whether or not it is in agreement and if it is not in agreement generating a fault signal that indicates that the memory cell is faulty, a fault analysis memory having a number of memory cells, and an address allocation circuit which receives address signals from the algorithmic pattern generator and performs address allocation for the fault analysis memory so that a number of memory cells of the memory under test correspond, based on a predetermined rule, to a single memory cell of the fault analysis memory.

Abstract: A digital audio signal demodulation circuit comprises a synchronous detection circuit (18) and a muting circuit (17) for muting the output from an interpolation circuit (16) using a synchronization lock signal generated from the synchronous detection circuit (18) when synchronization has been lost. The differential signal output from the interpolation circuit (16) is muted by the muting circuit (17) and thereafter integrated by an integration circuit (19). Thus, an audio signal with high sound quality can be demodulated without producing interruption noise even when synchronization has been lost or forcible muting is done.

Abstract: A programmable menu driven qualifier designed to make the abstract nature of small computer system interface (SCSI) definition easier to understand and work with. The qualifier is intended for testing and evaluating direct access and sequential access SCSI devices, such as disc drives and tape drives connected to the qualifier by an SCSI bus, the testing being carried out in accordance with ANSI SCSI-1 and ANSI SCSI-2 definitions. The qualifier is completely menu driven, and all commands are executed with a single keystroke of the keyboard. The qualifier uses a simple built-in concept which allows an operator quickly to become familiar with an SCSI protocol and command structure.

Abstract: A radio receiver (100) having a receiver section (103) receives and processes an information signal to provide received information having an error factor that varies at least with respect to operational parameters of the receiver section (103). In the radio receiver (100), a method is embodied for adaptively controlling the operational parameters of the receiver section (103) to optimize the error factor of the received information. The method (400, 400', 400") comprises operating in a first receiver mode in response to a predetermined mode select parameter, correlating a first signal recovered from the received information to at least a portion of a first code word to establish a first error criteria, and operating in the first receiver mode while the first error criteria does not exceed a predetermined error criteria.

Abstract: A diagnostic apparatus for testing devices such as computer systems, and computer system components such as disk drives or printers. The device comprises a main unit, the main unit having a central processing unit for executing instructions, issuing commands, and receiving data from a first device. The apparatus also has a first peripheral unit coupled to the main unit, the first peripheral unit having ports for interfacing with the first device, the first peripheral unit being interchangeable with a second peripheral unit for interfacing with a second device. The apparatus also comprises a first non-volatile memory unit coupled to the main unit, the first non-volatile memory unit comprising a first set of tests for the first device, the first non-volatile memory unit being interchangeable with a second non-volatile memory unit comprising a second set of tests for a second device. These interchangeable parts are provided so that the user may test various types of hardware.

Abstract: System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first group of data bits and a second group of data bits is first received from a CPU bus. The first group of bits is written to the first storage bits. In a "normal" mode, the second group of bits is written to the second storage bits. A set of check bits are calculated by the EDC circuit and written to the third storage bits. In the "swap" mode, the second group of data bits is stored in the third storage bits. "Alternate" bits are calculated by the EDC circuit, and written to the second storage bits. In memory reads, contents of all of the storage bits are received from the memory and directed to the error detecting circuit. The contents of the first storage bits are directed to error correction circuit.

Abstract: An event qualification architecture comprises event qualification cells (24) having an internal memory for detecting qualification events. The event qualification cells (24) output a signal indicating when a match has occurred, which is interpreted by an event qualification module (22). The event qualification module controls the test circuitry which may include test cell registers (14, 16) and test memory (28). A number of protocols are provided which can be designed into a circuit to provide the timing and control required to activate test logic in the circuit during normal system operation.

Abstract: System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough.