Abstract: An integrated circuit and a configuration method thereof are disclosed. The integrated circuit, applied to a neural network model calculation, includes a first operator engine, a second operator engine, a random access memory (RAM) and a direct memory access (DMA) engine. The first operator engine is configured to perform a first calculation operation. The second operator engine is configured to perform a second calculation operation. The DMA engine performs an access operation on the RAM according to a first memory management unit (MMU) table when the first operator engine performs the first calculation operation, and performs an access operation on the RAM according to a second MMU table when the second operator engine performs the second calculation operation.

Abstract: Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

Abstract: Devices and techniques for status management in storage backed memory are disclosed herein. An encoded message can be received at a first interface of the memory package. Here, the memory package also includes a second interface to a host. The message can be decoded to obtain a decoded message that includes an attribute. The attribute can be compared a set of attributes that correspond to an advertised status of the memory package. The comparison enables a determination that the attribute is in the set of attributes. The advertised status of the memory package can then be modified in response to the determination that the attribute is in the set of attributes.

Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing a first application image and a second application image in an application image memory, designating the first application image as active, receiving a first address for accessing the application image memory from a processor, modifying the first address based on a first offset between a base starting address of the first application image and a starting physical address of the first application image in the application image memory to generate a second address, and accessing the application image memory using the second address.

Abstract: Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

Abstract: A memory device can be operated with a set of refresh control features. A host can access the memory device to discover the set of refresh control features. The host can command the memory device to change at least one of the set of refresh control features. The memory device can be operated with the original and/or changed set of refresh control features.

Abstract: A hash table system, including a plurality of hash tables, associated with respective hash functions, for storing key-value pairs; an overflow memory for storing key-value pairs moved from the hash tables due to collision; and an arbiter for arbitrating among commands including update commands, match commands, and rehash commands, wherein for each system clock cycle, the arbiter selects as a selected command one of an update command, a match command, or a rehash command, and wherein the hash table system completes execution of each selected command within a bounded number of system clock cycles.

Abstract: An object of the present invention is to reduce deterioration in responsiveness to storage of content in a flash memory. A storage management apparatus according to the present invention includes a flash memory including a plurality of blocks each having a reserved area and a normal area, acquires a new dataset when a writable area included in a normal area of the plurality of blocks is larger than the new dataset and the new dataset is smaller in size than the writable area included in the normal area of the plurality of blocks in a case where unnecessary datasets included in the plurality of blocks are deleted, copies non-unnecessary datasets from the normal area of a specific block including the unnecessary datasets to the normal area of another block, deletes all datasets included in the normal area of the specific block, and stores the new dataset in the normal area of the specific block from which all the datasets are deleted.

Abstract: An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.

Abstract: A cache space management method and apparatus are disclosed. In the method, first, a hit rate of the read cache of the storage system is obtained; and then, a size of the read cache and a size of the metadata cache are adjusted based on the hit rate of the read cache. In the foregoing technical solution, the size of the read cache and the size of the metadata cache are dynamically adjusted by using the hit rate of the read cache as a decision factor. For example, when the hit rate of the read cache is relatively high, the size of the read cache may be increased.

Abstract: A storage device includes a non-volatile memory that stores a first original data and a first parity data, a storage controller that receives a second original data that differs from the first original data from an external storage device, and receives the first parity data from the non-volatile memory, and a computational engine that receives and computes the first parity data and the second original data from the storage controller, and restores a third original data that differs from the first original data and the second original data, wherein the storage controller receives the third original data from the computational engine and transmits the third original data to the host and the external storage device.

Abstract: Methods, systems, apparatus, and program products that can write auditable traces of a data wipe to a storage device are disclosed herein. One method includes performing, by a processor, a set of overwrite operations of a data wipe on a storage device, generating a set of auditable traces for the data wipe, and writing the set of auditable traces to the storage device. Systems, apparatus, and computer program products that include hardware and/or software that can perform the methods for writing auditable traces of a data wipe to a storage device are also disclosed herein.

Abstract: A data storage device and method for energy feedback and report generation are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to maintain an association between logical addresses and application identifiers of applications on a host; determine power implications associated with a command to access a logical address of the memory; generate a report on the power implications, wherein the report identifies an application identifier associated with the logical address; and provide the report to the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A system comprising a memory component including blocks, and a processing device, operatively coupled with the memory component. The processing device determines endurance values for the memory component. For each selected block of the plurality of blocks, the processing device determines an endurance estimation of the selected block based on at least one of a time to erase the selected block or an error statistic for the selected block, and updates an endurance value associated with the selected block based on the endurance estimation for the selected block. The processing device receives a write instruction to the memory component and distributes the write instruction to one or more of the blocks based on the endurance values. Other embodiments are described.

Abstract: A garbage collection process is performed in a storage system which comprises a storage control node, and storage nodes which implement a striped volume comprising a plurality of stripes having strips that are distributed over the storage nodes. The storage control node selects a victim stripe for garbage collection, and an empty stripe in the striped volume. The storage control node determines a data strip of the victim stripe having predominantly valid data based on a specified threshold, and sends a copy command to a target storage node which comprises the predominantly valid data strip, to cause the target storage node to copy the predominantly valid data strip to a data strip of the empty stripe which resides on the target storage node. The storage control node writes valid data blocks of the victim stripe to remaining data strips of the empty stripe, and releases the victim stripe for reuse.

Abstract: Techniques and mechanisms for identifying a memory access resource which is to be a target of an access request. In an embodiment, a processor comprises route tables which are to provide entries corresponding to different respective memory access resources which are coupled to the processor. The processor further comprises a list of items which each correspond to a different respective range of addresses, wherein the items each include an identifier of a respective route table, and an identifier of a respective index offset. Based on an address of the access request, a decoder circuit of the processor searches the list to identify a corresponding one of the items. In another embodiment, the decoder circuit accesses a route table entry, based on the search, to determine how the access request is to be directed to a particular memory access resource.

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. This increased bandwidth allows for multiple cache operations to be performed in parallel. In some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. In some examples, the hit logic may detect hits for each segment. That is, the hit logic does not correspond to a particular cache segment. Each address value may be serviced by any of the plurality of hit logic units.

Abstract: An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.

Abstract: Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.

Abstract: A convolution time de-interleaver includes an input buffer, an output buffer, a memory, an input control circuit, an output control circuit, and a controller. The memory includes a plurality of memory blocks. The input control circuit sequentially outputs a plurality of entries of data to a plurality of input register unit groups of the input buffer respectively and correspondingly. After a predetermined amount of data have been written to the input buffer, the controller writes part of data stored in the input buffer to a corresponding memory block. After the plurality of memory blocks are written, the controller writes data stored in a corresponding memory block to the output buffer. The output control circuit sequentially outputs a plurality of pieces of data stored in a plurality of output register unit groups of the output buffer.