Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10671913
    Abstract: The present disclosure provides a computation device and method, which are capable of using a single instruction to complete a transpose computation of a matrix of any size within constant time. Compared with conventional methods for performing a matrix transpose computation, the device and method may reduce the time complexity of a matrix transpose computation as well as making the usage of the computation simpler and more efficient.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 2, 2020
    Assignee: SHANGHAI CAMBRICON INFORMATION TECHNOLOGY CO., LTD
    Inventors: Shaoli Liu, Wei Li, Tian Zhi, Tianshi Chen
  • Patent number: 10671551
    Abstract: Systems, methods, and circuitries adapt a system-on-chip (SoC) for use with different external devices. In one example, an SOC includes a plurality of SoC data lanes configured to conduct data signals between the SoC and an external device interface. The SoC also includes an interface lane adaptor and a device interface including a plurality of interface connectors. The interface lane adaptor circuitry includes a plurality of SoC adaptor connectors connected to the interface connectors; a plurality of external adaptor connectors connected to the SoC data lanes and configured to be connected to the external device interface; a lane selector circuitry configured to connect a selected one of a first or a second SoC adaptor connector to a selected SoC data lane; and a lane configuration circuitry configured to control the lane selector circuitry to connect either the first or the second SoC adaptor connector to the selected SoC data lane.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Jiaxiang Shi, Vinay Sharma, Ingo Volkening
  • Patent number: 10664422
    Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a processing element communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the processing element via the first physical links. The first IC further comprises a data structure describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 26, 2020
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10657078
    Abstract: An indication of a capacity of a CMB elasticity buffer and an indication of a throughput of one or more memory components associated with the CMB elasticity buffer can be received. An amount of time for data at the CMB elasticity buffer to be transmitted to one or more memory components can be determined based on the capacity of the CMB elasticity buffer and the throughput of the one or more memory components. Write data can be transmitted from a host system to the CMB elasticity buffer based on the determined amount of time for data at the CMB elasticity buffer to be transmitted to the one or more memory components.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Maroney, Paul Suhler, Lyle Adams, David Springberg
  • Patent number: 10649927
    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
  • Patent number: 10642778
    Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 5, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Mohit Kishore Prasad, Richard Dominic Wietfeldt, Christopher Kong Yee Chun
  • Patent number: 10635631
    Abstract: The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 28, 2020
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Anargyros Krikelis
  • Patent number: 10628354
    Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Richard C. Murphy, Elliott C. Cooper-Balis
  • Patent number: 10628372
    Abstract: A simplified serial interface for a communications device. The serial interface includes an RF front end and a transmit block and at least one receive block located on different dies. The receive block is activated by a clock generator that is separate than the system clock. The at least one receive block can inhibit transmission of an enable signal to the receive block and inhibit operation of an oscillator of the interface.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 21, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: James Henry Ross, Matthew Lee Banowetz
  • Patent number: 10621123
    Abstract: Implementations are provided herein for systems, methods, and a non-transitory computer product configured to analyze an input/output (IO) pattern for a data storage system, to identify an application type based on the IO pattern, and to select optimal deduplication and compression configurations based on the application type. The teachings herein facilitate machine learning of various metrics and the interrelations between these metrics, such as past IO patterns, application types, deduplication configurations, compression configurations, and overall system performance. These metrics and interrelations can be stored in a data lake. In some embodiments, data objects can be segmented in order to optimize configurations with more granularity. In additional embodiments, predictive techniques are used to select deduplication and compression configurations.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: April 14, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay Dalmatov, Kirill Bezugly
  • Patent number: 10614010
    Abstract: A technique for handling queued interrupts includes accumulating, by an interrupt routing controller (IRC), respective backlog counts for respective event paths. The backlog counts track a number of events received but not delivered as interrupts to associated virtual processor (VP) threads upon which respective target interrupt handlers execute. An increment backlog (IB) message is received by the IRC. In response to receiving the IB message, the IRC determines an associated saturate value for an event path specified in the IB message. The IRC increments an associated backlog count for the event path specified in the IB message as long as the associated backlog count does not exceed the associated saturate value.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard L. Arndt, Florian A. Auernhammer
  • Patent number: 10613614
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Patent number: 10606776
    Abstract: Provided are a computer program product, system, and method for adding dummy requests to a submission queue to manage processing of queued requests according to priorities of the queued requests. A determination is made of a priority for a request to stage a track from the storage device to the cache or to destage a track from the cache to the storage device, comprising a first priority or a second priority. The first priority is higher than the second priority. At least one dummy request is added to a queue in response to the request having the second priority. The controller upon processing a dummy request in the queue discards the dummy request without performing an operation with respect to the storage device. An I/O request having the second priority is added to the queue. The controller processes the I/O request to stage or destage data.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: March 31, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 10599601
    Abstract: A single-wire bus (SuBUS) slave circuit is provided. The SuBUS slave circuit is coupled to a SuBUS bridge circuit via a SuBUS and can be configured to perform a slave task that may block communication on the SuBUS. Notably, the SuBUS slave circuit may not be equipped with an accurate timing reference source that can determine a precise timing for terminating the slave task and unblock the SuBUS. Instead, the SuBUS slave circuit is configured to terminate the slave task and unblock the SuBUS based on a self-determined slave free-running-oscillator count derived from a start-of-sequence training sequence that precedes any SuBUS telegram of a predefined SuBUS operation, even though the SuBUS operation is totally unrelated to the slave task. As such, it may be possible to eliminate the accurate timing reference source from the SuBUS slave circuit, thus helping to reduce cost and current drain in the SuBUS slave circuit.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: March 24, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala, Puneet Paresh Nipunage
  • Patent number: 10599429
    Abstract: Disclosed embodiments relate to a variable format, variable sparsity matrix multiplication (VFVSMM) instruction. In one example, a processor includes fetch and decode circuitry to fetch and decode a VFVSMM instruction specifying locations of A, B, and C matrices having (M×K), (K×N), and (M×N) elements, respectively, execution circuitry, responsive to the decoded VFVSMM instruction, to: route each row of the specified A matrix, staggering subsequent rows, into corresponding rows of a (M×N) processing array, and route each column of the specified B matrix, staggering subsequent columns, into corresponding columns of the processing array, wherein each of the processing units is to generate K products of A-matrix elements and matching B-matrix elements having a same row address as a column address of the A-matrix element, and to accumulate each generated product with a corresponding C-matrix element.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Mark A. Anders, Himanshu Kaul, Sanu Mathew
  • Patent number: 10599596
    Abstract: In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Jacob Jun Pan, Ashok Raj, Srinivas Pandruvada
  • Patent number: 10592422
    Abstract: A microprocessor has a data-less history buffer. Operands associated with a program instructions are stored in logical registers (LREGs) which are resolvable to physical registers that are not part of the history buffer. Register re-naming maintains integrity of data dependencies for instructions processed out of program order. The history buffer has pointers (RTAGs) to the LREGs. Entries in the history buffer are grouped into ranges. A mapper has a single port associated with each LREG, and each port receives data, from a single range of entries in the history buffer. Multiple entries, one from each range, may be restored concurrently from the history buffer to the mapper.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brian D. Barrick, Gregory W. Alexander, Dung Q. Nguyen
  • Patent number: 10592251
    Abstract: Register restoration using transactional memory register snapshots. An indication that a transaction is to be initiated is obtained. Based on obtaining the indication, a determination is made as to whether register restoration is in active use. Based on obtaining the indication and determining register restoration is in active use, register restoration is deactivated. To recover one or more architected registers of the transaction, a transactional rollback snapshot is created.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10585609
    Abstract: Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes a processor and a network interface having a tunneled network connection established with another network interface associated with another processor. The processor is configured to receive one or more packets indicating the network interface as a network destination and comprising a storage operation, and inspect at least a storage address included in a header of the one or more packets to determine that the storage operation corresponds to a storage drive managed by the other processor. The processor is configured to establish one or more further packets comprising the storage operation and having a header modified from the one or more packets to indicate a network address of the other network interface, and transfer the one or more further packets for delivery to the other network interface.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 10, 2020
    Assignee: Liqid Inc.
    Inventors: James Scott Cannata, Jason Breakstone
  • Patent number: 10587852
    Abstract: The present invention proposes a method for transmitting a broadcast signal. The method for transmitting the broadcast signal according to the present invention proposes a system capable of supporting a next-generation broadcast service in the environment for supporting a next-generation hybrid broadcast using a terrestrial broadcast network and an internet network. In addition, proposed is an efficient signaling method capable of covering both the terrestrial broadcast network and the internet network in the environment for supporting the next-generation hybrid broadcast.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: March 10, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Hyunmook Oh, Jongyeul Suh