Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10409743
    Abstract: Various implementations of a multi-chip system operable according to a predefined transport protocol are disclosed. In one embodiment, a system comprises a first IC comprising a memory controller communicatively coupled with first physical ports. The system further comprises a second IC comprising second physical ports communicatively coupled with a first set of the first physical ports via first physical links, and one or more memory devices that are communicatively coupled with the second physical ports and accessible by the memory controller via the first physical links. The first IC further comprises an identification map table describing a first level of port aggregation to be applied across the first set. The second IC comprises a first distribution function configured to provide ordering to data communicated using the second physical ports. The first distribution function is based on the first level of port aggregation.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 10, 2019
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 10409760
    Abstract: An adaptive interface high availability storage device. In some embodiments, the adaptive interface high availability storage device includes: a rear storage interface connector; a rear multiplexer, connected to the rear storage interface connector; an adaptable circuit connected to the rear multiplexer; a front multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the front multiplexer. The adaptive interface high availability storage device may be configured to operate in a single-port state or in a dual-port state. The adaptive interface high availability storage device may be configured: in the single-port state, to present a single-port host side storage interface according to a first storage protocol at the rear storage interface connector, and in the dual-port state, to present a dual-port host side storage interface according to the first storage protocol at the rear storage interface connector.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sompong Paul Olarig
  • Patent number: 10394725
    Abstract: A process may involve assembling a device at a device assembler. The process may include receiving a set of components, where each component of the set of components may be associated with a respective memory storing a set of characteristics of the component. The process may include assembling the set of components into the device at the device assembler. The process may also include accessing each respective memory of the components to read the sets of characteristics stored in the respective memories, and determining from the sets of characteristics of the components the characteristics of the device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: August 27, 2019
    Assignee: Dell Products, LP
    Inventors: Minchuan Wang, Bhyrav M. Mutnury, Stuart Allen Berke
  • Patent number: 10372662
    Abstract: A universal serial bus (USB) communication system includes a USB host that divides one data stream into first through (n)th sub-data streams and transmits the first through (n)th sub-data streams via first through (n)th USB host channels, respectively, a USB device that receives the first through (n)th sub-data streams via first through (n)th USB device channels, respectively and restores the data stream by combining the first through (n)th sub-data streams, and first through (n)th cables that are connected to the first through (n)th USB host channels via first through (n)th USB host ports and connected to the first through (n)th USB device channels via first through (n)th USB device ports. Here, the first through (n)th cables connect the first through (n)th USB host channels to the first through (n)th USB device channels, respectively.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cheon-Su Lee, Rohitaswa Bhattacharya
  • Patent number: 10366020
    Abstract: A data transfer control device includes an acquisition section, an analysis section, a band detection section, a mask output section and a selection section. The acquisition section acquires data from a plurality of processing sections for transmitting the data with a transmission path. The analysis section analyzes additional information of the data acquired by the acquisition section. The band detection section detects a transmission band of the transmission path based on the additional information. The mask output section outputs a request mask signal for suppressing the transmission of the data based on the transmission band detected by the band detection section and a target band preset on the transmission path. The selection section selects the data transmitted by the processing section based on the request mask signal output by the mask output section.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 30, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Tsutomu Ueta
  • Patent number: 10353844
    Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 16, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ofer Naaman, Zachary Kyle Keane, Micah John Atman Stoutimore, David George Ferguson
  • Patent number: 10353593
    Abstract: A method and apparatus for staged execution pipelining and allocating resource to staged execution pipelines are provided. One or more execution pipelines are established, where each of the one or more execution pipelines includes one or more execution stages. Data is provided to the one or more execution pipelines for processing and resources are allocated to the execution pipeline.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 16, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Nishanth Alapati, Pradeep Vincent, David Carl Salyers
  • Patent number: 10339071
    Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Debra Bell, Paul Glendenning, David R. Brown, Harold B Noyes
  • Patent number: 10331610
    Abstract: A universal asynchronous receiver/transmitter (UART) interface is disclosed. The UART interface may include a configurable asynchronous receiver and transmitter unit; and a configurable state machine, wherein the state machine allows configuration of the receiver and transmitter unit to support various baud rates and provide for start bit and stop bit configuration, wherein the state machine is further configurable to automatically support a plurality of communication protocols.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 25, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Roshan Samuel, Janmichael Aberouette, Ward Brown, Chintan Desai, Brant Ivey, Razvan Dochia
  • Patent number: 10333260
    Abstract: A device includes an interface configured to couple a power source to the device. The interface includes a plurality of contacts including at least one first contact configured to couple a voltage bus of the power source to a voltage bus of the device, and at least one second contact configured to couple the voltage bus of the power source to a secondary bus of the device. The device further includes a detector configured to determine a contact resistance of the at least one first contact based on a first current associated with the voltage bus and a second current associated with the secondary bus.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 25, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Robert A. Card
  • Patent number: 10331590
    Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Chris MacNamara, Tomasz Kantecki, John J. Browne
  • Patent number: 10324626
    Abstract: A control method of a control system includes storing output data to a memory according to a buffer pointer when a clock signal converts to a second level from a first level; storing input data to the memory according to the buffer pointer when the clock signal converts to the first level from the second level; and updating the buffer point.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: June 18, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventor: Chih-Lung Lin
  • Patent number: 10324885
    Abstract: A display device of an addin card generally includes, in structure, an addin card, a display device, a control board, and control software. The addin card is in information connection with the display device and the control board. The control software is loaded in the control board and is in information connection with the addin card. The display device access and reads hardware status data of the addin card, such as an operation temperature, a fan rotational speed, and a processing frequency. As such, in an attempt to observe the current hardware status data of the addin card, a user is allowed to make direct observation of the data on the display device without activating the control software. To change the operation performance of the addin card, the user may operate the control software to control the addin card, without entering BIOS, this being very convenient for the user.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: EVGA CORPORATION
    Inventor: Tai-Sheng Han
  • Patent number: 10324886
    Abstract: The invention relates to a holding device for securing at least one first expansion card in a rack server slot of one height unit. Incidentally, the holding device comprises a base body and a first holding tab, which is arranged on a first side of the base body. The first holding tab is configured to secure a riser card and a module to the holding device. Furthermore, the holding device comprises at least one second holding tab located on a second side of the base body opposite the first side. The at least one second holding tab is configured to secure a first expansion card to the holding device. Furthermore, the invention relates to an assembly having a holding device and a rack server slot of one height unit.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 18, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Gerhard Mühsam, Reinhard Salmen
  • Patent number: 10318394
    Abstract: A port controller includes an advertise block configured to determine a cable assembly coupled to the port controller is not compliant with a standard used by the port controller, a comparator configured to determine a current drawn from a power converter coupled to the cable assembly exceeds a capability of the power converter based on comparing a bus voltage to a threshold voltage, and a protection block configured to, in response to determining the current drawn from the power converter exceeds the capability of the power converter, cause the current drawn from the power converter to be reduced.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventor: William Robert Newberry
  • Patent number: 10318443
    Abstract: According to the computer device and the configuration and management method of a computer device that are provided in the embodiments of the present invention, an SMM and a CPU are controlled to connect to a PCIE Switch at different stages of system startup, so that management of a PCIE device does not rely on involvement of the CPU of the computer device. In this way, the PCIE device can be configured and managed without involvement of an operating system of the computer device, and CPU resources are saved. Manageability of the computer device is improved, meeting a requirement of a large data center for simplifying computing device management. In addition, the PCIE device is connected to the PCIE Switch by using a downstream port, with no need to configure a special interface to connect to the SMM, thereby simplifying system configuration.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Dexian Su
  • Patent number: 10311006
    Abstract: A peripheral module for connecting Highway Addressable Remote Transducer (HART) field devices provides different HART variables to the input area of its address space for cyclic reading by a CPU unit and continuously updates these HART variables, wherein a communication area for transmitting an individual HART variable is provided in the input and output area of the address space, where the CPU unit writes a command, which specifies the current HART variable to be read, into the output area of the communication area and the peripheral module provides and updates the specified HART variable in the input area of the communication area until a time at which the CPU unit writes a new command, which specifies another HART variable to be read, into the output area in order to make the transmission of all potentially available HART variables possible in a simple manner.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: June 4, 2019
    Assignee: Siemens Aktiengesellschaft
    Inventors: Carsten Langolf, Norbert Rottmann
  • Patent number: 10303642
    Abstract: An information handling system may include a first computing device, a second computing device, a connector device connecting the first computing device and the second computing device, and a controller. The connector device may be assembled from a set of components, where one or more of the components have a memory storing signal integrity characteristics for the component. The controller may be connected to the component memories, and may also be connected to the first computing device and the second computing device.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 28, 2019
    Assignee: Dell Products, LP
    Inventors: Minchuan Wang, Bhyrav M. Mutnury, Stuart Allen Berke, Harry C. Heinisch
  • Patent number: 10289593
    Abstract: A hot swap management device includes a bus buffer, a hot swap switch, and a controller. The bus buffer is selectively coupled to a host system management bus of a server. The hot swap switch is coupled to the bus buffer and a hardware expansion device. The controller is coupled to the bus buffer and the hot swap switch. When the hot swap management device is coupled to a board system management bus of the server, the controller assigns a hardware address to the bus buffer. A computational unit of the server controls the hardware expansion device through the host system management bus according to the hardware address.
    Type: Grant
    Filed: January 7, 2018
    Date of Patent: May 14, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventor: Po-Chung Chang
  • Patent number: 10289598
    Abstract: A described embodiment of the present invention includes a network having a first, second and third plurality of routers connected to a plurality of endpoints. At least one of the first plurality of routers includes a plurality of interposers having a number of queues. The at least one of the first plurality of routers has a demultiplexer for each interposer configured to receive multiplexed data from the interposer and provide demultiplexed data on to a plurality of second queues corresponding to the first queues of the number of queues. The at least one of the first plurality of routers also includes a number multiplexers, each of the number multiplexers having inputs configured to receive data from the number of queues.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: May 14, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Peter Yan, Alex Elisa Chandra, YwhPyng Harn, Xiaotao Chen, Alan Gatherer, Fang Yu, Xingfeng Chen, Zhuolei Wang, Yang Zhou