Patents Examined by Cheng-Yuan Tseng
  • Patent number: 10102888
    Abstract: A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction is to indicate a memory location and a register. The processor includes a memory access unit coupled with the decode unit and with the N-bit registers. The memory access unit is to perform a multiple register memory access operation in response to the multiple register memory access instruction. The operation is to involve N-bit data, in each of the N-bit registers comprising the indicated register. The operation is also to involve different corresponding N-bit portions of an M×N-bit line of memory corresponding to the indicated memory location. A total number of bits of the N-bit data in the N-bit registers to be involved in the multiple register memory access operation is to amount to at least half of the M×N-bits of the line of memory.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Bret Toll, Ronak Singhal
  • Patent number: 10102158
    Abstract: Methods and apparatus relating to the transfer of data for processing and/or the transfer of the resulting processed data are described. Some features relate to a processing system which performs data transfers under control of a Dynamic Sequence Controller (DSC). In various embodiments a sequence of operational codes is used to control data transfer with the status of data source and destination locations taken into consideration. Modification of the op code sequence used to control the dynamic sequence controller and thus the transfer of data can be performed asynchronously to control of processing units which can be controlled via a command and control bus used to control the function of operators which process the data provided via the data bus.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: October 16, 2018
    Assignee: Accusoft Corporation
    Inventor: Robert M Nally
  • Patent number: 10083136
    Abstract: An electronic component, a semiconductor package, and an electronic device including the electronic component and/or the semiconductor package are provided. The electronic component includes an electronic element; an encapsulation member that encapsulates the electronic element and has a first surface and a second surface substantially parallel to each other; and a lead electrically connected to the electronic element and extending outward from the encapsulation member. The lead is disposed entirely in a region between a plane of the first surface of the encapsulation member and a plane of the second surface of the encapsulation member.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam-ho Song, Teck-su Oh
  • Patent number: 10082957
    Abstract: A storage cartridge may include a storage controller comprising a single PCIe port and a PCIe switch. The PCIe switch may include a first PCIe port communicatively coupled to a first PCIe fabric, a second PCIe port communicatively coupled to a second, different PCIe fabric, and a third PCIe port communicatively coupled to the single PCIe port of the storage controller. The first PCIe port and the second PCIe port may be configured to be selectively communicatively coupled to a non-transparent bridge (NTB) of the PCIe switch.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 25, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Pinchas Herman, Vijay Karamcheti, Rodney N. Mullendore, William H. Radke
  • Patent number: 10083041
    Abstract: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventor: Mohammad Abdallah
  • Patent number: 10078361
    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 18, 2018
    Assignee: APPLE INC.
    Inventors: Karan Sanghi, Saurabh Garg, Haining Zhang
  • Patent number: 10067902
    Abstract: Techniques for determining an address of a management controller are provided. A microcontroller on a cartridge may read a signal from an enclosure, wherein the signal is associated with a slot in the enclosure. A network address for a first management controller associated with the cartridge may be determined based on the signal. The first management controller may be communicated with for cartridge management actions.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 4, 2018
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Leopoldo Alaniz, Andrew Brown
  • Patent number: 10067553
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Patent number: 10061729
    Abstract: A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 28, 2018
    Assignee: Ifineon Technologies AG
    Inventors: Albrecht Mayer, Joerg Schepers, Frank Hellwig
  • Patent number: 10055378
    Abstract: A device is connected to a connector of a computing system. In response, the computing system determines whether the device is a management device. In response to determining that the device is the management device, the computing system couples the connector to a management port of a service processor of the computing system. In response to determining that the device is not the management device, the computing system couples the connector to a system port of a primary processor of the computing system.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: August 21, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Shih-Chiang Chung, Chun-Hung Kuo
  • Patent number: 10042792
    Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 7, 2018
    Assignee: BiTMICRO Networks, Inc.
    Inventors: Amor Leo Saing Ricaborda, Alain Vincent Villaranda Abitria, Rose Fay M. Orcullo
  • Patent number: 10042795
    Abstract: Methods, systems, and computer program products are included for selecting, on the server computer, a selected host number that corresponds to the client computer; receiving, by the server computer, a network communication that includes a SCSI command, the network communication originating from the client computer; reading, by the server computer, a host number from the SCSI command; identifying, by the server, that the selected host number corresponds to the host number from the SCSI command; and preventing, by the server, the SCSI command from reaching a block I/O layer of the server computer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: August 7, 2018
    Assignee: Red Hat, Inc.
    Inventor: Laurence Oberman
  • Patent number: 10042805
    Abstract: A tunable bus-mediated coupling system is provided that includes a first input port coupled to a first end of a variable inductance coupling element through a first resonator and a second input port coupled to a second end of the variable inductance coupling element through a second resonator. The first input port is configured to be coupled to a first qubit, and the second output port is configured to be coupled to a second qubit. A controller is configured to control the inductance of the variable inductance coupling element between a low inductance state to provide strong coupling between the first qubit and the second qubit and a high inductance state to provide isolation between the first qubit and the second qubit.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 7, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ofer Naaman, Zachary Kyle Keane, Micah Stoutimore, David George Ferguson
  • Patent number: 10037293
    Abstract: A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: July 31, 2018
    Assignee: Nephos (Hefei) Co. Ltd.
    Inventors: Yi-Hung Chen, Yuan-Chin Liu
  • Patent number: 10037298
    Abstract: A user can set or modify operational parameters of a data volume stored on a network-accessible storage device in a data center. For example, the user may be provided access to a data volume and may request a modification to the operational parameters of the data volume. Instead of modifying the existing data volume, the data center can provision a new data volume and migrate data stored on the existing data volume to the new data volume. While the data migration takes place, the existing data volume may block input/output (I/O) requests and the new data volume may handle such requests instead. If a request is received for data not yet migrated to the new data volume, then the new data volume prioritizes a migration of the requested data.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: July 31, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Pieter Kristian Brouwer, Marc Stephen Olson, Nachiappan Arumugam, Michael Thacker, Vijay Prasanth Rajavenkateswaran, Arpit Tripathi, Danny Wei
  • Patent number: 10025739
    Abstract: An information processing system according to the present invention includes: a plurality of processing units; a plurality of input/output units controlled by any one of the processing units; a plurality of first connection units connecting one of the processing units to a first communication channel; a second connection unit connecting the input/output units to a second communication channel; a first mediating unit mediating the second communication channel and a communication network, and transmits identifiers of the input/output units via the communication network; and a plurality of second mediating units mediating a connection between the communication network and the first communication channel, receiving the identifier, and, when an identifier of its own is included in the received identifiers, establishing a connection between the input/output unit with the own identifier and the processing unit and detaches connections between the input/output unit with different identifier and the processing unit.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: July 17, 2018
    Assignee: NEC CORPORATION
    Inventor: Junichi Matsushita
  • Patent number: 10019405
    Abstract: A method and system are provided for transmitting SATA (serial advanced technology attachment) information. In an implementation, SATA commands are passed to an expander, rather than SCSI (Small Computer System Interface) commands. In an example implementation, SATA protocol elements are encapsulated into SAS (Serial Attached SCSI)-like frames and transmitted using the SSP (Serial SCSI protocol) and using SSP hardware.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: July 10, 2018
    Assignee: Microsemi Solutions (U.S.), Inc.
    Inventors: Neil Timothy Wanamaker, Timothy James Symons
  • Patent number: 10002003
    Abstract: A method for presenting initialization progress of hardware in a server, and a server where, before a basic input/output system (BIOS) runs to a preset process, an out-of-band central processing unit (CPU) in a hardware system in which a baseboard management controller (BMC) runs establishes a connection to a graphics card using a signal selection switch, the BIOS sends presentation information for representing initialization progress of hardware included in a server to the BMC, and then, the BMC presents the presentation information using the graphics card. Therefore, the presentation information can be always presented in an entire process in which the BIOS initializes the hardware in the server.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 19, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Fei Zhang, Jianfeng Yang
  • Hub
    Patent number: 9997939
    Abstract: A hub electrically connected to an electronic equipment and at least a portable device located in external environment is provided. The hub includes a first connector, at least a second connector, and a first DC/DC converter. The first connector is electrically connected to the electronic equipment, the second connector is electrically connected to the portable device. Data transmission between the portable device and the electronic equipment mutually is via the signal transmission line, the first connector, and the second connector. An input terminal of the first DC/DC converter is electrically connected to the electronic equipment, and an output terminal of the first DC/DC converter is electrically connected to the portable device, the first DC/DC converter is applied to output stable voltage to the portable device.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 12, 2018
    Inventor: Dong-Sheng Li
  • Patent number: 9996345
    Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 12, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Kristie Veith, Leonard Rarick, Manouk Manoukian