Abstract: There are provided a sensor data collection device, a sensor data collection system, and a method of collecting sensor data capable of reducing a drain of a battery due to standby power. The sensor data collection device includes a power supply, a power supply control circuit configured to control the power supply, a sensor configured to perform sensing to thereby obtain data, a memory configured to store the data obtained by the sensor, and a control circuit configured to control the power supply control circuit, the sensor, and the memory.

Abstract: Methods, systems, and devices for power management for a memory device are described. An apparatus may include a memory die that includes a power management circuit. The power management circuit may provide a voltage for operating a set of memory dies of the apparatus based on a supply voltage received by the memory die. The voltage may be distributed to the set of memory dies in the apparatus.

Abstract: An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Abstract: Provided are methods and systems for adaptive settings for a device. An example method can comprise utilizing a first configuration setting for a feature in a device, detecting a change in a device factor, and utilizing a second configuration setting for the feature in the device in response to the detected change. Another example method can comprise detecting a change in a device factor, activating a device feature, determining whether a change threshold has been exceeded, and updating a configuration setting for a device feature if the change threshold has been exceeded.

Abstract: One aspect provides a power sourcing equipment controller for providing power to a powered device using power-over-Ethernet (PoE). The power sourcing equipment includes a voltage-output logic block to output a sequence of voltage signals, the voltage signals comprising at least a detection signal and a classification signal; a current-measurement logic block to measure current provided responsive to the voltage signals; a backoff-time-determination logic block to determine a backoff time in response to the current-measurement logic block detecting the provided current exceeding a predetermined threshold, the backoff time being determined based on an amount of time needed for discharging an internal capacitor associated with the powered device; and a timing logic block to cause the voltage-output logic block to delay the output of a next sequence of voltage signals based on the determined backoff time, thereby facilitating powering up of a device compliant with a different PoE standard.

Abstract: A processor system includes a processor and a first memory area storing a boot program code. The boot program code starts execution of the operating system when executed by the processor, performs a cryptographic operation when processor executes the boot program code. A second memory area stores one or more cryptographic keys and is only accessible to the boot program code. A third memory stores the operating system. A communication interface receives data over a communication network. The processor retrieves the boot program code from the first memory area and executes the boot program code to start execution of the operating system. The processor terminates execution of the boot program code. The processor is configured to re-execute the boot program code while the operating system is executed to cryptographically encrypt data upon the basis of the cryptographic keys stored in the second memory area.

Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.

Abstract: A system for securely and reliably transferring startup script files over a network may include a unified extensible firmware interface (UEFI) network stack on a client server wherein the client server requests startup script over the network upon startup of the client server using a secure transfer network protocol and receives over the network the startup script. A computing device may comprise a unified extensible firmware interface (UEFI) shell to request a download of startup script, over a network, upon startup of the client server wherein the startup script is staged in a provisioned storage device within the client server to be mounted as local file systems in the client server. The UEFI shell.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: An example computing device includes a user interface, a network interface, a non-volatile memory, a processor coupled to the user interface, the network interface, and the non-volatile memory, and a set of instructions stored in the non-volatile memory. The set of instructions, when executed by the processor, is to perform a hardware initialization of the computing device according to a setting, establish a local trust domain and a remote trust domain, use a local-access public key to issue a challenge via the user interface to grant local access to the setting, and use a remote-access public key to grant remote access via the network interface to remote access to the setting.

Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

Abstract: Modern Standby configurations can be applied on a per-application basis. When a system is transitioning into Modern Standby, a host service can select a Modern Standby configuration to be applied to each Modern Standby capable application. The host service can then create job objects, or other suitable structures or functionality, to cause the selected Modern Standby configurations to be applied to the Modern Standby capable applications while the system is in Modern Standby. In this way, even though the operating system may implement Modern Connected Standby for all Modern Standby capable applications, dynamically selected Modern Standby configurations can be applied to mimic Modern Disconnected Standby or suspension for at least some of the Modern Standby capable applications.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: An information handling system includes a management controller configured to determine whether to initiate control of power consumption of a memory subsystem of the information handling system. A closed-loop memory thermal controller may receive temperature values to determine a temperature setpoint for the memory subsystem, and calculate an error value that is a difference between the temperature setpoint and a temperature measurement. If the error value is within a temperature margin, then the thermal controller may determine a proportional-integral power signal based on the temperature margin and the temperature measurement; and determine a proportional-integral gain based on a maximum rate of change of the temperature measurement between polling events of the temperature measurement and a polling rate of the temperature measurement.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine that an inventory of components of an information handling system (IHS) includes a first fan and an IHS card, which include a second fan; receive user input indicating a maximum acoustic sound pressure level (SPL); determine a first maximum fan speed for the first fan based at least on the maximum acoustic SPL; determine a first maximum power consumption for the IHS card and a second maximum fan speed for the second fan based at least on the maximum acoustic SPL; provide first configuration information, indicating the first maximum fan speed for the first fan, to a fan controller of the IHS; and provide second configuration information, indicating the first maximum power consumption and the second maximum fan speed for the second fan, to the IHS card.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: A method and system for intelligent power distribution management. Specifically, the disclosed method and system propose allocating (and deallocating) reserve or supplemental electrical power to host devices dynamically based on intelligent analyses of host device telemetry including, but not limited to, workload criticality, workload computing resource utilization, hardware configuration metadata, various operational parameters describing host device state, and measurements (as well as other information) pertinent to electrical power usage.

Abstract: A power distribution circuit for providing electric power from a plurality of power supplies to a plurality of loads comprises a combiner of power outputs of the power supplies to provide power at a given voltage to a plurality of hot swap modules that are each electrically connected to the combiner and to a power input of a corresponding load. Each hot swap module verifies one or more conditions selected from the given voltage being at least equal to a minimum voltage threshold, the given voltage not exceeding a maximum voltage threshold, and a current consumed by the load not exceeding a maximum current threshold. Each hot swap module delivers power to the power input of the corresponding load when all selected conditions are met and isolates the power input of the corresponding load from the power supplies when any one of the selected conditions is not met.

Abstract: A system includes a power disable circuit coupled to a bus connector of a host system and to power circuitry adapted to power on and off a memory device. The power disable circuit includes: source-coupled first FET and second FET with gates to receive a power disable (PWDIS) signal of the bus connector, wherein, in response to an asserted input of the PWDIS signal at a second gate of the second FET, a drain of the first FET is left floating; a latch circuit to assert an output in response to a general purpose input/output signal received from a processing device; and a third FET coupled to the drain of the first FET and to the output of the latch circuit, wherein in response to assertion of the output of the latch circuit, the third FET is to signal to the power circuitry to cut power to the memory device.

Abstract: An exercise information acquisition equipment of the present invention is an electronic equipment which builds therein a battery, is driven with electric power of the battery and acquires information relating to an exercise that a user performs and includes a battery remaining amount acquisition device which acquires a battery remaining amount of the battery, a time information acquisition device which acquires information relating to a time taken for the exercise which is information that how long the user plans to perform the exercise and an electric power control device which controls an operation pertaining to a power consumption reduction of the electronic equipment on the basis of the battery remaining amount and the information relating to the time taken for the exercise.