Abstract: A technique for reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by grouping the bond pads into a relatively small (compared to the total area of the die) sub-area within an interior area (generally away from the periphery) of the die. By keeping the bond pad layout small (tightly grouped, or oriented along a single row, or axis), differential thermally induced displacements between the bond pads are minimized, or are controlled in one dimension. Further, the bond pads may be disposed in a small area near the center of thermal expansion (centroid) of the die or near a heat-producing circuit element to minimize absolute thermal displacements of individual bond pads from the centroid or the circuit element. Overlapping sub-area patterns may be used, and grouped bond pads may be used in conjunction with (including overlapping of) traditional die-periphery located bond pads.

Abstract: A printed circuit board includes vibration areas where vibration sensitive components of an electrical circuit design fabricated on the printed circuit board are mechanically isolated from supporting circuitry. The present invention provides a printed circuit board with areas having an increased natural resonant frequency of vibration for the circuit board area where the vibration sensitive circuit is located. The printed circuit board comprises a number of slots, holes or other openings around the vibration sensitive circuitry. In addition, one or more circuit board conductive paths are provided for maintaining electrical conductivity between the isolated circuit and the supporting circuits.

Abstract: A circuit board having a thermal relief pattern for isolating heat generated during soldering of components thereon. The circuit board comprises (1) a substantially planar insulating substrate, the substrate having a via therethrough and (2) a substantially planar conductive layer located over the substrate, the via passing through the layer, the layer having a thermal relief pattern comprising a plurality of apertures located about the via, the plurality of apertures cooperating to restrict heat flow across the thermal relief pattern, each of the plurality of apertures having a boundary with the conductive layer free of discontinuities to inhibit edge effect electromagnetic resonance, the plurality of apertures defining a plurality of corresponding conductive bands in the conductive layer and between the plurality of apertures, the conductive bands cooperating to provide a predetermined minimum level of electrical conduction across the thermal relief pattern.

Abstract: A multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and a relatively high degree of wiring design freedom. These advantages are obtained in the inventive printed circuit board by electrically connecting power conductors or ground conductors using through holes. On the other hand, signal conductors in any two adjacent signal wiring layers are electrically connected using via holes extending only through an intervening electrically insulating layer. Preferably, the electrically insulating layer is a layer of photosensitive resin and the via holes are formed using conventional photolithographic techniques.

Abstract: The radiation noise suppression effect is enhanced by providing an insulation layer which is formed so that the circuit pattern is covered excepting at least a part of power source pattern or ground pattern on the substrate on which circuit pattern is formed, and a conductive layer which is formed so as to be connected to the uninsulated part of the power source pattern or the ground pattern on the insulation layer, by modifying pattern shape of the conductive layer and the insulation layer or by increasing or reducing the number of these layers.

Abstract: An electroless nickel plating is used as a primer for electroplating of copper. Preferably, electroless nickel plating is conducted after the surface of aluminum is subjected to nickel substitution with a nickel salt under a strongly acidic condition (pH: 1 or less). More preferably, the nickel substitution is carried out after the oxide film on the surface of aluminum is removed.

Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.

Abstract: A system and method for reducing coupled noise in a multilayer circuit board having signal lines disposed within a set of wiring channels on each of a plurality of the layers; and, a vias disposed within a set of via channels. According to a first embodiment, otherwise unused vias traverse the layers and are connected with otherwise unused signal lines to form electrical nets, thus reducing coupled noise throughout the module. In the context of the above-described environment, a method for reducing coupled noise includes the steps of determining the locations of unused ones of the wiring channels and unused ones of the via channels; providing shield lines disposed within the unused wiring channels and unused via channels; and, interconnecting the shield lines with one another and to a reference voltage by way of at least one terminating resistance.

Abstract: A semiconductor ceramic packaging substrate has the usual vias of sintered electrically conductive metal extending through the substrate. There are the usual metal conductor lines comprising conductive elements on the surface of the substrate. Each via is connected to the conductive elements in a predetermined pattern through a conductive via cap on the surface of the ceramic package. The caps join each conductive element and each via. The cap has a width substantially larger than the diameter of the via at the point of contact of the via and the conductive element in contact with it. The caps are also substantially thicker and wider than the conductive elements.

Abstract: An electrical contact and method for making an electrical contact allows a flat contact (404) to be formed early in the process of making an electronic device. The flat contact (404) is level with the remainder of the substrate (116) in which it is formed. The flat contact (404) does not interfere with any required subsequent process steps. The flat contact can be reflowed to form a ball contact (302) which protrudes above the top of the substrate (120) to which it is attached.

Abstract: The method of surface mounting radio frequency components includes using at least one radio frequency component having a pair of input/output contact points or areas at corners on the underside of the component, wherein each of the input/output contact points or areas abuts the adjoining edges of the corners. The component is positioned relative to a pair of traces on a circuit board for enabling an electrical connection thereto in a range of angular dispositions. By using a single non-customized component, adjacent components can be configured with a signal flow path of a range between about 0.degree. (a chain configuration) and about 180.degree. (a "U"-turn).

Abstract: A multilayer conductive wire is formed of a plurality of conductive layers stacked upon each other, and has a slit shaped groove extending in the direction intersecting the direction of stress in at least one conductive layer. With the groove mating with a protrusion in another conductive layer or a protrusion in an insulating film layer, a sliding phenomenon between the layers due to the stress can be restrained, so that a multilayer conductive wire free from destruction due to the sliding phenomenon caused by the stress and without losing conductivity can be provided.

Abstract: A wiring board comprising one or more inner layer circuit substrates and outer circuit layers formed from metal foil layers on both sides of said dinner layer circuit substrates via prepregs, said inner layer circuit substrate comprising an insulating layer and metal foil layers formed on both sides of said insulating layer, at least one inner layer circuit substrate or said outer circuit layers or both having hollow portions in the metal foil layer filled with an electroconductive substance, said wiring board having one or more through-holes at least in the hollow portions and filled with the electroconductive substance, has high reliability and a high wiring density.

Abstract: A terminal for an electric circuit device, comprises a copper core, a gold (Au) layer provided over the copper core, and a nickel (Ni) layer having the thickness of 1.5 .mu.m or less, provided under the gold (Au) layer. In another embodiment, the core is made of an alloy containing (Ni) and covered by a metallized surface layer made of copper.

Abstract: The inventive core for electrical connecting substrates, particularly for printed circuit boards and foil circuit boards, has an inner layer (I) with a columnar structure and on either side, metallic cover layers (A,A'), the columnar structure of the inner layer (I) comprising columns (9.1,9.2), which are regularly arranged, spaced from one another and from the cover layers (A,A'), being directed transversely to the service extension of the core and made from an electrically conductive material in a matrix (6) of an electrically insulating material. The cover layers (A,A') e.g. have electrical terminals (16,16', 17,17') in the form of through-plated blind holes (13,14) on selected columns (9) of the inner layer (I) and are structured in such a way that they have a regular pattern of terminals (16,16') on the facing cover layer and terminals (17,17') on the through-connections insulated from the cover layers, this grid pattern can have a size of approximately 0.5 mm.

Abstract: A large-current circuit board having a plurality of fasteners positioned and secured beforehand to the circuit board, and a plurality of busbars for electrically connecting the plurality of fasteners. Each of the plurality of busbars has a strip-like planar plate shape. Various ones of the plurality of fasteners may have the same or different distances from the surface of the circuit board. Specifically, the portions of the fasteners that are connected with the busbars may be at different heights so that plural busbars connecting the fasteners can cross each other at plural levels. A variety of fasteners and busbar securing boards may be used for electrically connectibly holding and securing the plurality of busbars with the plurality of fasteners on the circuit board.

Abstract: A method of making a multilayered circuit board wherein at least two layered subassemblies, each comprising a dielectric layer and at least one conductive layer therein, are bonded together. Each subassembly includes a through-hole extending therethrough which is aligned with a respective through-hole of the other prior to bonding. The subassemblies are compressed at a predetermined pressure (e.g., 300 psi) and then heated to a first temperature (e.g., 300.degree. C.) for an established time period, resulting in formation of a bond between the two through-holes. The resulting alloy formed from this bond possesses a melting point significantly greater than that of the subassembly dielectric (e.g., PTFE). Following this time period, the compressed subassemblies are heated to an even greater temperature (e.g., 380.degree. C.), again for an established time period, to assure dielectric flow. The subassembly is then cooled and the pressure removed.

Abstract: Ferrimagnetic structures formed of ferrimagnetic vias in a unitized multilayer microcircuit structure that is formed of a plurality of co-fired insulating layers.

Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.

Abstract: A method for reducing defects in an integrated circuit conductive lines characterized by the steps of providing a conductive line and contacting the conductive line with a layer which reduces stress in the line. There are several mechanisms by which the layer can accomplish the desired stress reduction. One method provides a resilient passivation layer over the conductive line and another method provides a resilient layer beneath the line. Yet another method creates a thin, flexible oxide layer over the conductive line. An extension of this latter method provides a resilient buffer layer over the thin oxide layer and a thick oxide layer over the resilient layer. Another form of stress-reducing layer includes an anti-diffusion layer which reduces the diffusion of metal atoms of the conductive layer into the surrounding oxide. A conductive line structure of the present invention includes at least one conductive line and at least one layer contacting the conductive line which reduces stress in the line.