Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent semiconductor fin; recessing the isolation feature to form a recess; forming a metal-containing compound mask in the recess; depositing a stress layer over the metal-containing compound mask, such that the stress layer is in contact with a top surface of the metal-containing compound mask; and annealing the metal-containing compound mask when the stress layer is in contact with the top surface of the metal-containing compound mask.

Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Abstract: The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.

Abstract: Methods of reducing wafer bowing in 3D DRAM devices are described using a 3-color process. A plurality of film stacks are formed on a substrate surface, each of the film stacks comprises two doped SiGe layers having different dopant amounts and/or Si:Ge ratios and a doped silicon layer. 3D DRAM devices are also described.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.

Abstract: A drying method of a polyimide paste which can maintain a printing shape while maintaining productivity includes an organic solvent and a polyimide resin dissolved in the organic solvent, and which becomes cured polyimide by being cured as a result of being dried and heated, the drying method including a step of applying the polyimide paste to a surface of a base material, a step of applying a solvent including a polar material to a surface of the base material at least at a portion where the polyimide paste is applied, and a step of, after applying the solvent including the polar material, drying the polyimide paste and the solvent including the polar material.

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

Abstract: An HEMT device of a normally-on type, comprising a heterostructure; a dielectric layer extending over the heterostructure; and a gate electrode extending right through the dielectric layer. The gate electrode is a stack, which includes: a protection layer, which is made of a metal nitride with stuffed grain boundaries and extends over the heterostructure, and a first metal layer, which extends over the protection layer and is completely separated from the heterostructure by said protection layer.

Abstract: A memory cell comprising a substrate, a bit line vertically oriented from the substrate along a first direction, a nanosheet transistor including at least one nanosheet horizontally oriented from the bit line along a second direction perpendicular to the first direction, and a capacitor horizontally oriented from the nanosheet transistor along the second direction.

Abstract: A memory device including a substrate; a bit line laterally oriented to be parallel to the substrate; a transistor including two channels that are laterally oriented from the bit line and a word line that is vertically oriented and surrounds the two channels; and a capacitor laterally oriented from the transistor.

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

Abstract: A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions maybe modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.