Patents Examined by Christina Sylvia
  • Patent number: 10446664
    Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device, wherein the fabrication operations include forming a stack over a substrate. The stack includes alternating layers of sacrificial nanosheets and channel nanosheets over a substrate. The stack further includes lateral sidewalls having a length (L) and end sidewalls having a width (W), wherein L is greater than W. Source or drain (S/D) regions are formed along the length (L) of the lateral sidewalls.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10438875
    Abstract: A dual-chip package structure is configured to electrically connect a first CS bonding pad of a non-volatile memory chip to a CS pin of a lead frame and electrically connect a second CS bonding pad of a volatile memory chip to a heat-dissipating exposed pad, so as to provide a non-volatile memory chip select signal for the non-volatile memory chip through the CS pin, and provide a volatile memory chip select signal for the volatile memory chip through the heat-dissipating exposed pad. This achieves a low pin count dual-chip package structure, which can effectively reduce the cost and avoid conflict between the two chips.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: October 8, 2019
    Assignee: LYONTEK INC.
    Inventor: Chi-Cheng Hung
  • Patent number: 10431696
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion and a first nanowire over the first fin portion. The first nanowire has a polygonal cross-section. The semiconductor device structure also includes a first gate structure surrounding the first nanowire, and two first source/drain portions adjacent to the first nanowire.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
  • Patent number: 10410797
    Abstract: A method for fabricating a solar cell is provided and has steps of: providing a transparent conductive substrate; forming a porous supporting layer on the transparent conductive substrate; forming a porous conductive counter electrode layer on the porous supporting layer, where the porous conductive counter electrode layer includes a carrier blocking layer and a conductive layer, and the carrier blocking layer is between the porous supporting layer and the conductive layer; and providing a light-absorbing material penetrating from the porous conductive counter electrode layer. The light-absorbing material fills within the porous supporting layer through a plurality of pores in the porous conductive counter electrode layer.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 10, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Chao-Yu Chen, Tzung-Fang Guo, Wei-Chih Lai
  • Patent number: 10410923
    Abstract: A method of processing a wafer includes forming a mask on portions of a face side of the wafer which correspond to devices; performing plasma etching on the face side of the wafer through the mask to etch areas of streets other than areas thereof corresponding to metal components, thereby forming grooves in the areas of the streets to a depth corresponding to a finished thickness of device chips; bonding a protective member for protecting the face side of the wafer, holding the face side of the wafer on a chuck table through the protective member and grinding a reverse side of the wafer until bottoms of the grooves are exposed, to fragmentize the wafer into the device chips; and picking up the device chips from the protective member, leaving remaining regions of the substrate which correspond to the metal components on the protective member.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: September 10, 2019
    Assignee: DISCO CORPORATION
    Inventor: Hideyuki Sandoh
  • Patent number: 10396178
    Abstract: Method and structure of forming a vertical FET. The method includes depositing a bottom source-drain layer over a substrate; depositing a first heterostructure layer over the bottom source-drain layer; depositing a channel layer over the first heterostructure layer; depositing a second heterostructure layer over the channel layer; forming a first fin having a hard mask; recessing the first and the second heterostructure layers to narrow them; filling gaps with an inner spacer; laterally trimming the channel layer to a narrower width; depositing a bottom outer spacer over the bottom source-drain layer; depositing a high-k layer on the bottom outer spacer, the first fin, and the hard mask; and depositing a metal gate layer over the high-k and top outer spacer to produce the vertical FET. Forming another structure by recessing the metal gate layer below the second inner spacer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tenko Yamashita, Chen Zhang
  • Patent number: 10388611
    Abstract: A semiconductor device has a substrate and a semiconductor component disposed over the substrate. A discrete electrical device can be disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor component. A ferromagnetic material is disposed over the encapsulant. The ferromagnetic material includes one or more ferrite type materials or other material having a crystalline structure exhibiting ferromagnetic properties. The ferromagnetic material includes a ferromagnetic film with a polyethylene terephthalate layer, ferrite layer, and adhesive layer. The ferromagnetic film is provided from the sheet of ferromagnetic films. A shielding layer is formed over the ferromagnetic material and around the semiconductor component.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 20, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Sungwon Cho, Seonhong Choi, Changoh Kim
  • Patent number: 10388614
    Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hyun Lee, Kyoung Moo Harr, Seung Yeop Kook, Ji Hoon Kim, Young Gwan Ko
  • Patent number: 10388651
    Abstract: A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with a pitch P. The first and second regions are separated by an isolation region with spacing S, wherein S is greater than P. A first insulating layer is deposited and recessed to a target depth in the first region, and to a second depth in the isolation region. The second depth is lower than the target depth. A first etch stop layer is formed over the recessed first insulating layer, and a second insulating layer is formed over the first etch stop layer to increase a level of insulating material in the isolation region to the same target depth in the first device region. The recessed first insulating layer, first etch stop layer, and second insulating layer form a uniform thickness shallow trench isolation layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Bruce Miao, Xin Miao
  • Patent number: 10388540
    Abstract: This invention relates to cooling devices for multi-chip semiconductor devices, system-on-a-package devices, and other packaged devices. Because of the non-uniform height across the surface in such large-chip and multi-chip assemblies, providing heat exchange can be troublesome. Many air cooled heat sinks are too stiff to adapt to such non-uniform or warped shapes of chips or to shape-changing chip surfaces during operation. In the present disclosure, application of a mechanical load perpendicular to the chip plane causes certain features to flex and adapt to the non-uniform height of the chip plane, providing improved heat exchange.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Thomas Brunschwiler, Ingmar Meijer, Stephan Paredes, Gerd Schlottig
  • Patent number: 10361202
    Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chan Suh, Gi-gwan Park, Dong-woo Kim, Dong-suk Shin
  • Patent number: 10358742
    Abstract: A method of growing a conductive Ga2O3-based crystal film by MBE includes producing a Ga vapor and a Si-containing vapor and supplying the vapors as molecular beams onto a surface of a Ga2O3-based crystal substrate so as to grow the Ga2O3-based crystal film. The Ga2O3-based crystal film includes a Si-containing Ga2O3-based single crystal film. The Si-containing vapor is produced by heating Si or a Si compound and Ga while allowing the Si or a Si compound to contact with the Ga.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: July 23, 2019
    Assignees: TAMURA CORPORATION, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto
  • Patent number: 10355209
    Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Katsunari Obata, Hiroshi Kawasaki
  • Patent number: 10354985
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Patent number: 10355029
    Abstract: A switching element, a manufacturing method thereof, an array substrate and a display device are provided. The switching element includes: a base substrate; a first thin-film transistor (TFT), disposed on the base substrate; and a second TFT, disposed on the first TFT, wherein the first TFT includes a first electrode and a second electrode, and the first TFT and the second TFT share the first electrode and the second electrode.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 16, 2019
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Liqing Liao, Hongmin Li, Ying Wang, Dong Wang
  • Patent number: 10347544
    Abstract: Techniques are disclosed for fabricating co-planar p-channel and n-channel gallium nitride (GaN)-based transistors on silicon (Si). In accordance with some embodiments, a Si substrate may be patterned with recessed trenches located under corresponding openings formed in a dielectric layer over the substrate. Within each recessed trench, a stack including a buffer layer, a GaN or indium gallium nitride (InGaN) layer, and a polarization layer may be selectively formed, in accordance with some embodiments. The p-channel stack further may include another GaN or InGaN layer over its polarization layer, with source/drain (S/D) portions adjacent the m-plane or a-plane sidewalls of that GaN or InGaN layer. The n-channel may include S/D portions over its GaN or InGaN layer, within its polarization layer, in accordance with some embodiments.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: July 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Sanaz Gardner, Seung Hoon Sung
  • Patent number: 10347659
    Abstract: A display panel is described. Further, an electroluminescent display panel and a display device are described. By arrangement of a second signal bus line, a first end of a first signal line in a first display area in the display panel is electrically connected with the first signal bus line, and the second end of the first signal line is electrically connected with a first conducting wire in the second signal bus line, so that uniformity of a signal input by the first signal line in the first display area can be ensured. Therefore, the structure is not only the precondition of ensuring signal uniformity of the first display area, but is also the precondition of ensuring signal uniformity of a display area of the entire display panel.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: July 9, 2019
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Kerui Xi, Tingting Cui, Zhonglan Cai, Zuzhao Xu
  • Patent number: 10333094
    Abstract: Optoelectronic device comprising an organic active layer provided for generating electromagnetic radiation, and first and second electrodes contacting the active layer. The second electrode has a second electrode layer. The first electrode comprises a first electrode layer and a first connection layer spaced at least in places from the first electrode layer, with the active layer being arranged at least in places therebetween, and through vias extend through the active layer and form an electrical contact between the first electrode layer and the first connection layer. The through vias form a contiguous through via structure that subdivides the second electrode layer into a plurality of sub-regions which are spaced from one another and wherein the contiguous through via structure subdivides the active layer into a plurality of regions which are separate from one another. In operation, the through vias are electrically conductively connected to one another directly.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: June 25, 2019
    Assignee: OSRAM OLED GmbH
    Inventor: Thomas Wehlus
  • Patent number: 10304700
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 28, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Shih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10297551
    Abstract: A method of manufacturing a redistribution circuit structure and a method of manufacturing an INFO package at least include the following steps. An inter-dielectric layer is formed over a substrate. A seed layer is formed over the inter-dielectric layer. A plurality of conductive patterns are formed over the seed layer. The seed layer and the conductive patterns include a same material. While maintain a substantially uniform pitch width in the conductive pattern, the seed layer exposed by the conductive patterns is selectively removed through a dry etch process to form a plurality of seed layer patterns. The conductive patterns and the seed layer patterns form a plurality of redistribution conductive patterns.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh