Patents Examined by Christina Sylvia
  • Patent number: 10930558
    Abstract: A processing apparatus includes: a holding unit that holds a workpiece; a processing mechanism that processes the workpiece held by the holding unit; a processing liquid supplying mechanism that supplies a processing liquid containing an oxidizing agent to at least the workpiece held by the holding unit at the time of processing the workpiece by the processing means; a processing waste liquid recovery section that recovers a processing waste liquid containing the processing liquid supplied from the processing liquid supplying mechanism to the workpiece; a discharge passage through which the processing waste liquid is discharged from the processing waste liquid recovery section to the outside of the processing apparatus; and a waste liquid treatment mechanism that is disposed in the discharge passage and that decomposes the processing liquid contained in the processing waste liquid while the processing waste liquid flows through the discharge passage.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 23, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kenji Takenouchi
  • Patent number: 10930560
    Abstract: A method for creating a detachment area in a solid, in particular for detaching the solid along the separating region. Said solid portion that is to be detached is thinner than the solid body from which the solid portion has been removed. Said method preferably comprises at least the following steps: the crystal lattice of the solid is modified by means of a modifying agent, in particular by means of at least one laser, in particular a pico- or femtosecond laser. The modifications, in particular the laser beams penetrate into the solid via a surface of the solid portion which is to be detached, several modifications are created in the crystal lattice, said crystal lattice penetrates, following said modifications, in the areas surrounding the modifications, at least in one particular part.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: February 23, 2021
    Assignee: Siltectra GmbH
    Inventors: Christian Beyer, Jan Richter
  • Patent number: 10930651
    Abstract: A semiconductor device includes a substrate including a first area and a second area, and first and second transistors formed in the first area and the second area, respectively. The first transistor includes a first gate insulating layer on the substrate, a first TiN layer on the first gate insulating layer contacting the first gate insulating layer, and a first filling layer on the first TiN layer. The second transistor includes a second gate insulating layer on the substrate, a second TiN layer on the second gate insulating layer contacting the second gate insulating layer, and a second filling layer on the second TiN layer. A threshold voltage of the first transistor is less than that of the second transistor, the second gate insulating layer does not comprise lanthanum, and an oxygen content of a portion of the first TiN layer is greater than that of the second TiN layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju Youn Kim, Se Ki Hong
  • Patent number: 10923465
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Patent number: 10916485
    Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 9, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Soon Wei Wang, Jin Yoong Liong, Chee Hiong Chew, Francis J. Carney
  • Patent number: 10910250
    Abstract: The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 2, 2021
    Assignee: Soitec
    Inventors: Marcel Broekaart, Ionut Radu, Didier Landru
  • Patent number: 10892228
    Abstract: Methods of manufacturing a conductive feature and a package are provided. One of the methods includes the following steps. A seed layer is formed. A conductive pattern is formed over the seed layer. The seed layer and the conductive pattern include a same material. A dry etch process is performed to partially remove the seed layer exposed by the conductive pattern, to form a seed layer pattern. A plasma treatment process is performed on the seed layer pattern and the conductive pattern thereon, wherein the step of partially removing the seed layer and the step of performing the plasma treatment process are in-situ processes.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Jung Tsai, Hung-Jui Kuo, Yun-Chen Hsieh
  • Patent number: 10883953
    Abstract: Described examples include a sensor device having at least one conductive elongated first pillar positioned on a central pad of a first conductor layer over a semiconductor substrate, the first pillar extending in a first direction normal to a plane of a surface of the first conductor layer. Conductive elongated second pillars are positioned in normal orientation on a second conductor layer over the semiconductor substrate, the conductive elongated second pillars at locations coincident to via openings in the first conductor layer. The second conductor layer is parallel to and spaced from the first conductor layer by at least an insulator layer, the conductive elongated second pillars extending in the first direction through a respective one of the via openings. The at least one conductive elongated first pillar is spaced from surrounding conductive elongated second pillars by gaps.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 5, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Vikas Gupta
  • Patent number: 10867811
    Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
  • Patent number: 10867988
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit comprises a silicon on insulator (SOI) device separated from a SOI substrate by an insulation layer. The SOI device comprises a power supply terminal, a ground terminal, a first I/O terminal and a second I/O terminal. An electrostatic discharge (ESD) protection circuit is integrated with the SOI device. The ESD protection circuit is configured to shunt current between two terminals of the SOI device during an ESD surge event. An electrostatic discharge (ESD) enhancement circuit is integrated with the SOI device. The ESD enhancement circuit is configured to clamping the SOI substrate to a lower potential of the two terminals of the SOI device.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sheng-Fu Hsu
  • Patent number: 10854710
    Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 1, 2020
    Assignee: SOCIONEXT, INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 10854551
    Abstract: A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-Jung Yu, Kyung Suk Oh
  • Patent number: 10854449
    Abstract: A method of forming a silicon film in a recess formed in a target substrate includes: preparing a target substrate having a recess in which a plurality of different bases is exposed; forming an atomic layer seed on at least an inner surface of the recess by sequentially supplying a raw material gas adapted to the plurality of different bases and a reaction gas reacting with the raw material gas to the target substrate one or more times while heating the target substrate to a first temperature; and forming a silicon film on a surface of the atomic layer seed so as to fill the recess by supplying a first silicon raw material gas to the target substrate while heating the target substrate to a second temperature.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Satoshi Takagi, Hiroyuki Hayashi, Hsiulin Tsai
  • Patent number: 10847552
    Abstract: An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 24, 2020
    Assignee: INNOLUX CORPORATION
    Inventors: Tsung-Han Tsai, Yuan-Lin Wu
  • Patent number: 10840221
    Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ilsoo Kim, Heeyoub Kang, Young-Rok Oh, Kitaek Lee, Hwi-Jong Yoo
  • Patent number: 10832948
    Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu Hee Han, Jong Min Baek, Viet Ha Nguyen, Woo Kyung You, Sang Shin Jang, Byung Hee Kim
  • Patent number: 10825989
    Abstract: A vapor deposition mask includes a metal mask and a resin mask having an opening. An inner wall surface for composing the opening has an inflection point in a thicknesswise cross section of the resin mask. When an intersection of a first surface, not facing the metal mask, of the resin mask and the inner wall surface is set to be a first intersection, an intersection of a second surface, facing the metal mask, of the resin mask and the inner wall surface is set to be a second intersection, and there is set a first inflection point first positioned from the first intersection toward the second intersection, an angle formed by a line connecting the first intersection and the first inflection point and the first surface is larger than an angle formed by a line connecting the first inflection point and the second intersection and the second surface.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 3, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Katsunari Obata, Hiroshi Kawasaki
  • Patent number: 10818727
    Abstract: A semiconductor device includes a gate structure on a substrate, source and drain contacts respectively on opposite sides of the gate structure and connected to the substrate, a magnetic tunnel junction connected to the drain contact, a first conductive line connected to the source contact, and a second conductive line connected to the first conductive line through a first via contact. The second conductive line is distal to the substrate in relation to the first conductive line. The first and second conductive lines extend in parallel along a first direction. The first and second conductive lines have widths in a second direction intersecting the first direction. The widths of the first and second conductive lines are the same. The first via contact is aligned with the source contact along a third direction perpendicular to a top surface of the substrate.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoungsu Son, Seung Pil Ko, Jung Hyuk Lee, Shinhee Han, Gwan-Hyeob Koh, Yoonjong Song
  • Patent number: 10818659
    Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction, and parallel gate structures intersect the fins in a second direction perpendicular to the first direction. Also, source/drain structures are positioned on the fins between the gate structures, source/drain contacts are positioned on the source/drain structures, sidewall insulators are positioned between the gate structures and the source/drain contacts (wherein the sidewall insulators have a lower portion adjacent to the fins and an upper portion distal to the fins), and upper sidewall spacers are positioned between the upper portion of the sidewall insulators and the source/drain contacts.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Guowei Xu, Scott Beasor
  • Patent number: 10818781
    Abstract: Provided is a heterojunction bipolar transistor (HBT) structure with a bandgap graded hole barrier layer, including: a sub-collector layer including an N-type group III-V semiconductor on a substrate, a collector layer on the sub-collector layer and including a group III-V semiconductor, a hole barrier layer on the collector layer, a base layer on the hole barrier layer and including a P-type group III-V semiconductor, an emitter layer on the base layer and including an N-type group III-V semiconductor, an emitter cap layer on the emitter layer and including an N-type group III-V semiconductor, and an ohmic contact layer on the emitter cap layer and including an N-type group III-V semiconductor. Bandgaps of the hole barrier layer at least include a gradually increasing bandgap from the base layer towards the collector layer and a largest bandgap of the hole barrier layer is greater than bandgap of the base layer.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 27, 2020
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Kai-Yu Chen